( DVcon 05 Item 9 ) --------------------------------------------- [ 10/25/05 ]
Subject: TransEDA vNavigator, Cadence HDLScore, Synopsys CoverMeter
CODE COVERAGE -- For 3rd party coverage tools, TransEDA holds the lead, but
lives the life of a clever monkey playing in a tree below a pack of lions.
2005 - What do you think of Verisity SureCov and TransEDA and Summit
HDLScore vs. the built-in coverage in Synopsys VCS, Cadence NC,
Mentor ModelSim, Aldec?
Cadence built-in (HDLScore) : #################################### 36%
Verisity SureCov : ####### 7%
Synopsys (CoverMeter) : ###################################### 38%
Mentor MTI built-in coverage : ####################### 23%
Aldec built-in coverage : ### 3%
TransEDA vNavigator : ############### 15%
If TransEDA slips once, those built-in code coverage tools inside of VCS,
NC-Sim, and ModelSim will eat TransEDA for lunch. Ouch! Cadence HDLScore,
Verisity SureCov, and Synopsys CoverMeter have no problems whatsoever because
they're protected parts of Cadence or Synopsys.
Always looking at ModelSim as possible replacement for TransEDA, but
TransEDA keeps adding more functionality.
- Greg Tumbush of Starkey Labs.
We use TransEDA. If the Cadence built-in coverage tool could achieve
the same level as dedicated tool, we'd love to choose built-in.
- Stone Shi of STmicroelectronics
We typically use the ModelSim coverage tool. When that gives us
problems we use TransEDA HDLcover (w/o the formal stuff). Without
fault coverage you need something like this to make sure that your
code is tested functionally.
- [ Kenny from Southpark ]
We use the built-in code coverage of Mentor's ModelSim and Cadence's
NC-Sim. In the past we used TransEDA's Verification Navigator. It's
too slow (2x) compared with the simulators. I think the faster of the
simulators is sufficient. Code coverage is not as meaningful by
itself anyway.
- [ An Anon Engineer ]
Synopsys VCS built-in, Undertow.
- Marshall Johnson of Movaz Networks
We just use the build-in coverage in VCS
- Tuan Luong of Integrated Device Technologies
SureCov is better and easy to use.
- [ An Anon Engineer ]
TransEDA. The ModelSim tool could edge out TransEDA in the flow.
But the ModelSim coverage tool is not good enough, yet.
- William Mills of Northrop Grumman Corp.
We have TransEDA tools but never have enough time in the project to
use them to do fault coverage.
- [ An Anon Engineer ]
We use Spyglass and TransEDA VN-Cover. We've been happy with
Spyglass, but there are some holes in it's clock domain crossing
checks. We have been less happy with VN-Cover because it's
performance sucks and it's Verilog 2001 support is not up to snuff.
- [ An Anon Engineer ]
We used to use TransEDA for code coverage, but the built-in VCS
coverage is faster and cheaper, so we use that now. So far,
the bugs encountered have not overcome the speed & price benefits.
- Jonathan Craft of McData Corp.
We have been using vNavigator from TransEDA. We are looking at the
ModelSim capability.
- [ An Anon Engineer ]
TransEDA VN-Cover for code coverage. Leda for Linting.
- [ An Anon Engineer ]
We started using VCS for code coverage (line, conditional, FSM, toggle).
Earlier it used to be HDLScore. But looks like VCS needs to stabilize
in terms of code coverage. Lot of issues reported and getting resolved
in the past few months.
- [ An Anon Engineer ]
We use SureLint and SureCov. The built-in coverage in NC is missing a
few key usability features in analysis, but we expect to move to NC
when those are addressed.
- [ An Anon Engineer ]
HDLScore is OK. SureCov does not do it.
- [ An Anon Engineer ]
Have used SureCov via the PLI and VCS built-in coverage. Neither can
carry filters forward as the code changes. Had to create our own tool
to do this.
- [ An Anon Engineer ]
SureCov is useful during unit or module testing, but not as useful
for full chip verification.
- [ An Anon Engineer ]
Leda + Synopsys built-in coverage tool.
HDLScore is a pain. The infrastructure requirements are a burden that
Synopsys built-in coverage tool blew out of the water. Once we saw
what Synopsys was doing we didn't even think about running NC-Sim on
our project. Now that Cadence has built-in there coverage tool, we
think they are back on track.
- [ An Anon Engineer ]
We use the VCS built-in coverage tool. This is adequate for our needs.
- [ An Anon Engineer ]
Have used SureCov & liked it. Currently use Synopsys CoverMeter.
- [ An Anon Engineer ]
We also used the built-in line coverage tool for VCS. It is still an
immature product and Synopsys was somewhat less responsive in dealing
with it. Does anyone have a tool that can deal with code changes
without having to rerun all the coverage?
- [ An Anon Engineer ]
We use TransEDA and prefer it over the basic ModelSim. We also use
HDL Design Manager.
- Jeff Clark of Starkey Labs
We use ModelSim built in coverage and Specman vManager.
- [ An Anon Engineer ]
Use built-in ModelSim.
- Rainer Mueller of Oasis SiliconSystems AG
For simulation code coverage, we use TransEDA vNavigator.
- Tony Lanier of Harris Corp.
Have TransEDA coverage but use built-in coverage in ModelSim.
- [ An Anon Engineer ]
SureCov is, from my experience, by far the best of these tools. I wish
we were using it now.
- [ An Anon Engineer ]
We are evaluating SureCov.
- [ An Anon Engineer ]
Cadence NC built-in coverage, but really relying on explicitly coded
functional coverage in Specman. Still some TransEDA usage.
- Bob Warren of STmicroelectronics
Use TransEDA. Cadence and ModelSim do offer some of the features, but
still lack metrics which TransEDA had years ago, and they are not
keeping up with the pace of development. However, they come free with
the simulators in some cases, so there is pressure to use them instead.
- [ An Anon Engineer ]
HDLScore is not so easy to use. Cadence HAL not workin so good and
rules are hard coded in the tool (its not really possible to have our
own rules. We use Mentor Design Analyst.
- [ An Anon Engineer ]
We use HDLScore, as it is very integrated in the Cadence Incisive stuff.
- [ An Anon Engineer ]
TransEDA VNCover
- [ An Anon Engineer ]
We have used TransEDA in the past. But we will be moving to Cadence's
coverage which comes with ncsim simulator. Integrating TransEDA with
Cadence tools, though possible, was time consuming.
- Samuel Irlapati of Unisys
In the past we used HDLScore for RTL coverage. Now, we use the built-in
coverage tool in Synopsys VCS and feel it is good enough for us.
- [ An Anon Engineer ]
TransEDA adds some additional functionality, but ModelSim is advancing
in their offerings.
- [ An Anon Engineer ]
For coverage the built-into Synopsys VCS works just fine. It's amazing
what's given in VCS these days. Talk about cheaper/better/faster.
- Rajen Ramchandani of Mindspeed Technologies
We use the built-in RTL code coverage in VCS. It works. I don't get
real excited about code coverage.
- John Zook of Stargen
I like Synopsys coverage tool integrated with VCS. Especially the
functional coverage part of Vera.
- Azeez Chollampat of PLX Technology
Have used Synopsys VCS built-in coverage (found it not very useful).
- [ An Anon Engineer ]
We have been using the assertion and code coverage built into VCS, and
functional coverage built into Vera. Both work well.
- John Stiles of Silicon Logic Engineering
Cadence's code coverage tool. For us, the code coverage is a small
part of our overall coverage strategy. The ease of integration and
deployment with the built-in coverage tools makes it an easy decision
to use over other vendor's tools. We will always use the built-in
tools based on what I see now.
- [ An Anon Engineer ]
We are using the built-in VCS code coverage tool. It is adequate for
our needs.
- Ian Perryman of Altera
We use built-in coverage tool in VCS and NC-Verilog. For both tools,
it was very dificult to merge some results generated with the different
simulation model (such as PCB model, or module level model, etc.)
- Masato Inogai of Fujitsu
We use the built-in coverage of VCS. It works well - especially the
sensitized condition coverage (almost as important as line coverage).
We moved from ASICs to FPGAs in our last set of chips. (BTW, now we
are moving back toward Structured Arrays and ASICs.) Even with FPGAs,
we found it important to do assertions and code coverage. There was
an initial thought that without the painful cost of ASIC respin, we
did not need to do code coverage and assertions. However, it is still
easier to find the tough corner cases in simulation than in the lab.
Lab debug of very large FPGAs is slow and serial. It can only handle
a few bugs a month. A month of code coverage can save a year of lab
debug.
One feature we would really like to see added to the VCS code coverage
tool is a redundant code checker. Many of the uncovered lines and even
more of the uncovered conditions are not POSSIBLE to reach -- due to
coding "style" or actual coding mistakes. A significant amount of time
is spent determining which lines are unreachable from external stimulus
of the Device Under Test. The industry already has semi-formal tools
that can look for unreachable code. It would be nice if a semi-formal
tool could be mated to the VCS code coverage tool to check these lines
and conditions when they are deemed uncovered to see if they are
actually impossible to cover.
- Dan Joyce of Hewlett-Packard
We have in the past used VHDLcover which we found useful. In future we
will use the ModelSim in-built coverage tool.
- [ An Anon Engineer ]
We are currently use TransEDA code coverage tool. My understanding
is that the Mentor ModelSim built-in tool has few probelms.
- [ An Anon Engineer ]
We use VCS built-in coverage tool. Were using Cadence HDLScore before.
They are both the same; buggy and inaccurate and unstable.
- [ An Anon Engineer ]
For coverage we use Cadence NC-Verilog built-in coverage tool ICT.
- [ An Anon Engineer ]
ModelSim and TransEDA code coverage.
- [ An Anon Engineer ]
We use built-in coverage from VCS. It has been fairly powerful, albeit
a little clumsy. It takes some experience to learn how to apply the
results thoroughly, especially the state coverage. It is clumsy around
modules that are instantiated multiple times and used differently.
It's also overly pessimistic identifying false warnings for FSM resets.
- [ An Anon Engineer ]
Used to use SureCov, which was great. For $$ reasons, now use built-in
Cadence stuff, which is not great.
- Andrew Peebles of Cortina Systems
We use the built-in capability of ModelSim, have not compared to other
tools.
- [ An Anon Engineer ]
Currently using ModelSim code coverage tool.
- [ An Anon Engineer ]
I've only used SureCov so far. Unfortunately coverage measurement is
still last on the schedule priority. That keeps us from moving to
full constrained random test generation.
- George Gorman of LSI Logic
I'd go for Verisity SureCov, but other vendors may do as well.
It is a money issue, for they provide the same functionality.
- [ An Anon Engineer ]
We use HDLScore. HDLScore and SureCov type dedicated tools are much
better than the built-in covreage offered by Synopsys VCS.
- [ An Anon Engineer ]
We have used HDLScore on 5 ASICs. We will see how code coverage runs
on the MTI 6.0 release. In general the large vendors have not been
able to compete with the smaller vendors on this type of tool.
- Tom Paulson of Qlogic
We use to use SureCov until VCS started including it built-in. VCS
coverage is easier to setup because it is already integrated into the
simulator, but the actual tool was still awkward on the 7.1 release.
Since we now had the same number of coverage licenses as simulator
licenses, using the VCS coverage was a great value proposition for us.
- Kea Hunt of Nazomi Communications
We use Novas nLint for linting. We use the built-in coverage checkers
in VCS and ModelSim.
- [ An Anon Engineer ]
I have used TransEDA extensively in the past and for the simple level
at which we were running the tools I find the built-in Cadence code
coverage to be as effective.
- [ An Anon Engineer ]
Traditionally we've used TransEDA's vNavigator for coverage, but it's
increasingly difficult to find versions of vNavigator and NC-Sim
that work together and produce correct results. Also, generating a
coverage report which aggregates support across a large test suite is
becoming a big problem - the runtime seems to be proportional to the
square of the number of tests, which is resulting in summary runs
taking stupid amounts of runtime.
I suspect that we will end up moving towards the NC-Sim built-in
coverage tool as soon as someone gets around to stitching it into our
flow; however, at first glance, it's reports seem to be more difficult
to read than vNavigator's.
- [ An Anon Engineer ]
HDLScore is our standard coverage tool, but I haven't used it yet.
- Jan Johnson of Rockwell Collins, Inc.
We are using CoverMeter in VCS. It seems to work pretty well and not
slow down our sims too much.
- Dan Steinberg of Integrated Device Technology
Honestly, I write a lot of code while I am on the road in hotel rooms
or visiting family. I use the free tools Wellspring Veriwell and
Altera Quartus Web Edition to do basic lint checks for missing ports,
undeclared signals, missing semicolons, etc.
My current project is not yet being verified with coverage, but it
will be soon, and probably using whatever is built-in to NC-Sim.
- Jonah Probell, consultant
Vnavigator from TransEDA.
- Pascal Gouedo of STmicroelectronics
We tried to use HDLScore from Cadence but it is broken for mixed
language environments. Crashed the whole tool.
- [ An Anon Engineer ]
We use the ICTR which is now build in NC-Sim for coverage and HAL
for linting. The integration of ICTR into NC-Sim is not ready yet,
so we are missing the FSM coverage. But I think they work on that.
HAL is OK for pure linting, too.
- [ An Anon Engineer ]
We are moving to the integrated code coverage in NC because it is WAY
easier to use.
- [ An Anon Engineer ]
Code coverage is done in VCS, but its utility is limited.
- [ An Anon Engineer ]
We had an old tool to do our coverage, but I forgot what it was. I
mostly use ModelSim's built-in coverage.
- Tom Mannos of Sandia National Labs
Coverage: TransEDA. They need to be proactive to keep their
advantages vs. the market.
- [ An Anon Engineer ]
Use Cadence built-in for coverage. No need to buy a coverage tool, as
all major simulators now have it built-in.
- [ An Anon Engineer ]
I used SureCov til a year ago but this tool is dead now that all
the Verilog simulators have a code coverage tool integrated. Plus
Verilog 2001 support at that time was really poor. Verisity didn't
seem to have any interest in SureCov anymore anyway. Same for
Surelint. Then I used HDLScore a bit and was quite happy with it.
- [ An Anon Engineer ]
We're using Mentor ModelSim for dynamic coverage.
- Tom Moxon of Moxon Design
Currently use HDLScore but planning to change to inbuilt VCS coverage.
- [ An Anon Engineer ]
Built-in coverage in VCS works well enough, have used HDLScore in the
past. We're more interested in our functional coverage reports right
up until the end when we peruse the code coverage outputs of VCS.
- [ An Anon Engineer ]
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