( DVcon 05 Item 8 ) --------------------------------------------- [ 10/25/05 ]
Subject: Cadence HAL, Synopsys Leda, Atrenta Spyglass, 0-In CheckList
LINTERS -- As usual, the most popular non-built-in linter people yarped
about using was Atrenta Spyglass. Lots of engineers like it, but it still
has a tough uphill fight against those *free* built-in linters.
2005 - "What linter/debug/coverage tools do you use? ... vs. the built-in
... What about Synopsys Leda, Cadence HAL or Mentor DesignAnalyst
or Atrenta SpyGlass?"
Cadence built-in (HAL) : ################################ 32%
Verisity SureLint : ### 3%
Synopsys built-in lint : ##################### 21%
Synopsys Leda : ################## 18%
Synopsys Verilint : ### 3%
Mentor MTI built-in lint : ################## 18%
Mentor DesignAnalyst : ## 2%
0-In CheckList lint : #### 4%
Aldec built-in lint : ### 3%
Atrenta Spyglass : ################## 18%
Novas nLint : #### 4%
TransEDA vnCheck : ## 2%
Veritools HDLlint : .5 %
One surprise this year was how Synopsys Leda broke out from being just a
purely Synopsys-only linter. I found lots of Cadence and ModelTech users
who *paid* to have the Leda linter in their toolset. That is, Leda's not a
freebie built-in for them, they paid extra for it. Users actively wanting
Leda is a *major* turnaround because 2 years ago Leda was one of the more
poorly rated (by users) tools in the entire Synopsys product line. To go
from laughing stock to a near Spyglass peer (both at 18%) is impressive.
Oh, yea, and I can't get over how 0-In CheckList came into the linting
business out of left field. I didn't see that one coming, either.
We have been doing more FPGA designs than ASIC of late. Interestingly
enough, the FPGA compilers seem to provide quicker (and more readable)
lint feedback than the linter's do. Go figure.
- Mike Bly of World Wide Packets
0-In CheckList as a linter. We also still run the "retired" Surelint
since they occasionally find different things. We used SureCov but
are moving more to the built-in simulator coverage tools since code
coverage is not really all that interesting and using the free
version gives just as much info.
- Kevin Jones of Rambus
We found 0-In CheckList extremely helpful as a linter, esp. the CDC
reporting which found real problems in some IP we brought in from a
3rd party.
- [ An Anon Engineer ]
We use 0-In CheckList mainly to look at clock crossing checks.
- [ An Anon Engineer ]
We're starting to use Leda. No, that's not quite the right thing to
say. More accurately, we're starting to debug Leda.
- Matt Weber of Silicon Logic Engineering, LLP
For linting, we use Spyglass; for code coverage, Cadence NC's ICT,
and form functional coverage, Vera.
- [ An Anon Engineer ]
Used Leda in a previous life on the design description. Fast and
revealing. Liked all but the price.
- Jan Johnson of Rockwell Collins, Inc.
TransEDA Vncheck for rule/lint. It's an excellent replacement if you
are used to Verilint. Both Cadence HAL and Mentor Design Analyst
evaluations failed. Synopsys came in at $30k, and TransEDA came in
at $10k.
- Brien Anderson of Siemens Medical
For linter, switched from TransEDA VnCheck to Leda.
- [ An Anon Engineer ]
Leda. The good point is that it comes with many rules which are
organized in a sensible way. You can also add custom rules, although
the rule language is pretty inscrutable and we need Synopsys help to
write custom rules.
The bad points are that Leda runs very slowly (we compare it against
old Verilint, and Synopsys hates when we make that comparison), and
the bug rate is quite high compared to DC, PT, and Formality.
- John Busco of Nvidia
We currently use in house linting (very basic). We will be looking
at Mentor Design Analyst which we think could improve our code quality
and integrate well with our other Mentor tools.
- [ An Anon Engineer ]
We use Leda.
- Harpreet Singh of STmicroelectronics
We use Novas nLint for linter. Cadence Simvision/Novas Debussy for
debug.
- [ An Anon Engineer ]
Linter: Verilint. It does the job, no great push to move to anything
else.
- Niels Reimer of Agilent
Verilint. Cadence HAL is OK, too.
- Justin Spangaro of Spangaro Systems
HAL now and moving to Leda. HDLScore is better than native NC-Sim
coverage.
- [ An Anon Engineer ]
We're using Cadence HAL.
- Stefano Traferro of STmicroelectronics
HAL currently use. Not so easy to put in place.
- [ An Anon Engineer ]
We use HAL and 0-In CheckList.
- [ An Anon Engineer ]
We use Atrenta Spyglass for linting. Cadence's HAL is good for name
convention checking, etc., but we don't use it. Cadence's tool is
simple with a command line interface and GUI. Atrenta's seems to be
better, but no command line interface. Nice GUI.
- [ An Anon Engineer ]
Started using Cadence HAL recently. Good tool.
- John Gray of Atmel
We use HAL, don't know the other ones. Our goal is to catch typos
before checkin in a new revision of a file. So the LINT tool needs
to be fast and cover those basics not covered by RTL simulation
(there are many).
HAL unfortunately generates way too many messages so we wrote a Perl
script to filter it's log file thus reducing it to 1/10th the size,
which is still 2,000 lines!!! So the next level is that we run HAL
on the version before and after making the RTL changes and then only
look at the differences (all scripted).
That seems to be the most effective way of using HAL.
In the old days we used to have Verilint. This was a crapy buggy tool,
but it was fast and didn't produce enormous log files. So overall
Verilint was much better to work with then the current HAL.
Unfortunately Verilint is no more.
- Jean-Paul van Itegem of Philips Semiconductors
We use HAL & Spyglass
- [ An Anon Engineer ]
We use Verilint. Also use the DC-Elaborate function from dc_shell.
Leda is on our radar screen because I think it has advantage in
analyzing constraints that will work/not work well for DC.
- [ An Anon Engineer ]
We will be using Leda which I think is just an average tool.
- Sandro Pintz of Portal Player, Inc.
We are (still) using Surelint. Looked at Leda at one point but didn't
move forward because of its price.
- Henry So of Mobilygen
Leda is partially helpful
- [ An Anon Engineer ]
We use Leda.
- Dave Ferris of Tundra Semiconductor
We use Synopsys Leda (painful but effective) & CoverMeter.
- [ An Anon Engineer ]
Using built-in tools in Cadence HAL
- [ An Anon Engineer ]
We have been trying to use Leda, but running into a number of problems
with the tool.
- John Stiles of Silicon Logic Engineering
Using Leda for rtl code linting.
- [ An Anon Engineer ]
For linting, we use Synopsys Leda.
- Tony Lanier of Harris Corp.
We use Leda, but honestly, the jury is still out on it's real
effectiveness.
- [ An Anon Engineer ]
We have also started to use Leda in addition to prior and current use
of VN-Check for lint checking.
- K.C. Buckenmaier of Hifn, Inc.
We use Spyglass but are not that happy with the delivered quality.
Synopsys Leda is no option at the moment.
- [ An Anon Engineer ]
For lint, we use HDLLint from Everest Design Solutions. It is small,
but quick, and easily run from the command line or from inside emacs.
Our designers detest GUIs. However, I believe they are strongly
considering moving to Novas's nlint tool.
- John Zook of Stargen
We've tried Leda. For Verilog it is great because of all of the
trouble that you can get into with that language. For VHDL it's a
joke, Leda doesn't even catch simple things.
- [ Kenny from Southpark ]
Synopsys CoverMeter is good enough.
Leda had issues but now its fine. We need to look at other tools.
- [ An Anon Engineer ]
We use Leda. We have some custom rules and use a subset of the supplied
rules. Using linting has virtually eliminated gate/rtl mismatches. We
still use equivalence checking but the mismatches have been areas where
we ignored Leda warnings.
- [ An Anon Engineer ]
Novas' nLint. VCS code coverage.
- [ An Anon Engineer ]
We use Novas nLint, but we're not very happy with it. Its not been
an important enough tool in our flow to force change, though.
- Jonathan Craft of McData Corp.
We are still using Verilint for linting.
- [ An Anon Engineer ]
Verilint and Spyglass.
- Mark Lancaster of Freescale Semiconductor
Use Spyglass regularly. Have some use of Debussy.
- [ An Anon Engineer ]
We use Atrenta Spyglass for Lint. It works OK.
- Dan Joyce of Hewlett-Packard
We have used Spyglass, but use Leda because of our integrated flow.
- Dave Ferris of Tundra Semiconductor
We use Atrenta Spyglass. We also use Verdi.
- Juan Carlos Diaz of Agere Systems
Our vendor has in the past given us a time-limited Spyglass license,
with custom scripts. We found this helpful and will use it again if
offered, but probably not if we'd have to buy a license ourselves.
- Frank Vorstenbosch of Telecom Modus Ltd.
These tools are just an expensive replacement for properly training
engineers not to write bad code to begin with.
- Michiel Vandenbroek of China Core Technology Ltd.
Spyglass/Debussy/TransEDA. Not tried any of these design entry tools.
- Karthik Kandasamy of Wipro
We use a combination of Spyglass and TransEDA for linting and coverage.
Spyglass is a relatively new tool for us so I can't really comment on
it yet. We find TransEDA gives a good insight into test coverage,
although it does give the odd bizarre result.
- [ An Anon Engineer ]
We're using Mentor DesignAnalyst at the present as a linter.
- Tom Moxon of Moxon Design
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