( DVcon 05 Item 7 ) --------------------------------------------- [ 10/25/05 ]
Subject: IBM Sugar/PSL, 0-In CheckerWare, Verplex OVL, System Verilog SVA
NO CLEAR LEADER -- Assertions hit that tipping point of 53% adoption back
in 2004; this year it's 58%. Yawn. The interesting story here is that
there's no clear consensus as to exactly which flavor of assertions to use.
2004 - "What do you think of assertion languages and assertion
libraries such as SVA, PSL, OVL, 0-In CheckerWare?"
don't use : ############################################### 47%
IBM Sugar/PSL : ################################## 34%
0-In CheckerWare : ################## 18%
System Verilog SVA : ####### 7%
Synopsys Vera OVA : ####### 7%
Verplex OVL : ################# 17%
2005 - "What do you think of assertion languages and assertion
libraries such as SVA, PSL, OVL, 0-In CheckerWare?"
don't use : ########################################## 42%
IBM Sugar/PSL : ##################### 21%
0-In CheckerWare : ######## 8%
System Verilog SVA : ################## 18%
Synopsys Vera OVA : ############ 12%
Verplex OVL : ############## 14%
VHDL Assertions : ## 2%
It's interesting to see how Sugar/PSL and the proprietary 0-In assertions
dropped ~1/2 in 2005, while SVA and OVA picked up ~2X in 2005.
Have used PSL, OVL, 0-In. Now trying out SVA. 0-In assertions are
tied to their proprietary tool, so no good. 0-In also needed a lot of
handholding to get going and Mentor support has not been great.
Currently use PSL and are exploring SVA more. Found bugs with PSL,
so it is much better than busy work.
- Brad Sonksen of QLogic
We're using SVA. I expect new RTL to be as littered with assertions
as the Wisconsin countryside is littered with cheese shops & taverns.
- Matt Weber of Silicon Logic Engineering, LLP
We tried OVA for our functional coverage will little success. We
still use 0-In Checkers. We plan to use SVA in our next project.
- [ An Anon Engineer ]
Assertions are great help, too bad it is too slow. We are starting
to use Sugar PSL to check our 'parallel case' statements. That is
very valuable because in many cases it is very hard to verify the
correctness of such statements.
- Jean-Paul van Itegem of Philips Semiconductors
We use PSL along with a static PSL assertion checking tool quite
extensively. IBM's Odyssey (RuleBase). All our IP bus interfaces are
checked against a standard set of rules, and some of our simpler IPs
are verified exclusively with PSL assertions, and no functional
simulation at all.
We're looking at embedding PSL assertions into the RTL for use in
NC-Sim, but I don't think we've done it seriously yet.
- [ An Anon Engineer ]
PSL. It should be used, but as yet no clear business reason to push
users into coding with PSL.
- Bob Warren of STmicroelectronics
We are looking into PSL in a big way. Right now they are toys that
sometimes work.
- [ Kenny from Southpark ]
We have used Sugar/PSL in the past but never in anger. However, it
did prove useful. I plan on using PSL assertions to add some extra
confidence to our simulations (using the built-in assertion in
ModelSim 6.0) on my current project. However we will not be buying
any dedicated property checking tools... yet.
- [ An Anon Engineer ]
assertion languages - no.
- Elchanan Rappaport of Lynx Photonic Networks
After years of talking about it, we're finally really using SVA and
PSL assertions for design-intent and protocol checking, but not for
full formal verification.
- [ An Anon Engineer ]
We are using OVA.
- Peng Hong of Datang Microelectronics China
We are just starting to use PSL. Looked at OVA, it's ugly.
- [ An Anon Engineer ]
I wrote about 30 OVA assertions for a 1,000 line design that attached
to a purchased PCI core. We found 1 real bug and 1 spec ambiguity.
The total time commitment was about 2 days, including learning the
assertion language which I felt was very good return. These were
executed in VCS.
- [ An Anon Engineer ]
Our current verification platform is TestBuilder/C++ and OVL.
- Jeffrey Ebert of Sonics, Inc.
We use OVL, and are moving to SVA. They seem to be useful for
catching bugs. OVL is simple enough to use (with similar gadgets
made for SVA) that the overhead really isn't bad.
- [ An Anon Engineer ]
We have limited use of OVL.
- Niels Reimer of Agilent
Currently we use OVL, because its free. PSL could be the future.
- [ An Anon Engineer ]
OVL is good enoguh. Assertion languages generate "bulky" assertions
and are impossible to prove using formal verif techniques.
- [ An Anon Engineer ]
PSL is nice but SVA is better, especially in a System Verilog
environment. Two nice features of SVA unavailable in current PSL
are action blocks and the ability so conditionally compile different
SVA assertions through the use of Verilog's `ifdef compiler
directives. I currently use SVA and they are extremely useful.
- Cliff Cummings of Sunburst Design
We're trying SVA for the first time in the current project.
- Christian Mautner of Integrated Device Technologies
We are using SVA in our designs. I must confess that as this is the
first design in which we are incorporating assertions. It has been a
little slow. However, they have been useful in both detecting problems
and measuring coverage after the initial ramp-up.
- [ An Anon Engineer ]
Assertion libs help designers not familiar with assertions get
acclimated. We've been using OVL and hope to move to SVA. We've
found many bugs with assertions and find them very useful.
- Jonathan Craft of McData Corp.
I am pushing for SVA which I think is useful. I am cautioning my team
not to go overboard with it because you might easily end up designing
the same thing twice!
- Sandro Pintz of Portal Player, Inc.
My preference is SVA. The best usage is going to be on the interfaces
between designers that have a lot of signal interaction between the
blocks. It definitely speeds up debug of failures when an assertion
fires. But, we've also had our share of false positives that have
slowed down the verification effort.
- Dan Steinberg of Integrated Device Technology
Currently using SVA, even though the rest of the design is Verilog.
- John Stiles of Silicon Logic Engineering
We are using SVA is a small scale. Hoping to use it in larger scale.
- Henry So of Mobilygen
We've always used VHDL assertions - one of the many reasons we used
VHDL instead of Verilog. So this is not a completely new thing...
ModelSim supports PSL, and is just starting to support SVA.
Currently we're starting to use PSL as it seems to be better
supported at present. Because SVA supports most of the
functionality of Vera (randomness, etc.) we'll likely switch over
to it as it becomes completely supported in ModelSim.
- Tom Moxon of Moxon Design
We're a mix of OVA and SVA. Designers haven't cared about using them,
but they've saved our verification team many hours of debug time.
Still learning about how to use them most effectively.
- [ An Anon Engineer ]
Started using Sugar PSL and OVA. Not clear yet as to the advantages.
You have to debug the assertions, too!
- John Gray of Atmel
I have never used assertion checking before but do plan to use it in
my next project. A team here used Cadence PSL for verifying some of
the blocks of our last ASIC. It appears to work fine.
- [ An Anon Engineer ]
We use Sugar PSL and also the internal language of Averant's Solidify
tool, HPL.
- [ An Anon Engineer ]
For getting started, OVL is perfect. OVA is on its way out and should
not be used. PSL/SVA will dominate the future and I see all major
companies supporting both equally over time.
0-In provides a nice technology, but given the standard languages and
available libraries, the additional cost of 0-In is not worth it. 0-In
as we know it today will go away within the next 5 years.
- [ An Anon Engineer ]
We have found assertions to be very useful. Currently most of our
assertions are home grown using VHDL and its' assert command. We are
playing with PSL and while there is a learning curve we think this is
our longer term approach. Hopefully vendor support will continue to
increase and more assertions libraries in PSL will become available.
- [ An Anon Engineer ]
We will most probably use PSL in out next project. Since we have a lot
off re-usable code, PSL makes more sense. It can be used inline and
looks more vendors support it, so we will be more portable.
- Samuel Irlapati of Unisys
Have experimented a little with assertions but have not been able to get
engineers to adopt them. Effort vs. benefit is still not very clear.
- [ An Anon Engineer ]
We use 0-In Assertions. However, if you only have time for assertions
or code coverage, pick code coverage. It packs more bang for the buck
(corner case bugs for the engineering effort).
- Dan Joyce of Hewlett-Packard
OVL. Definetely useful.
- [ An Anon Engineer ]
We currently use SVA as an easy step forward from OVL. It's useful. It
looks like PSL has more overall momentum, though, so we'll probably
switch to that to minimize language syntax proliferation. Some people
feel that PSL is more for verification engineers while SVA is more for
design engineers. It's a pity that SVA isn't simply a design subset of
PSL. But since it isn't we'll probably stick to PSL for both purposes.
- [ An Anon Engineer ]
We're using 0-In Assertions. There was initial reluctance on the part
of some of our team to add the assertions, but they ultimately proved
their worth. Not only do they uncover bugs, but they provide a good
way to measure functional coverage.
- [ An Anon Engineer ]
We use 0-In assertions. I would say that our current maturity with the
0-In tools puts us at 50% efficiency. In some instances the assertions
have little to no value. In some instances they are essential.
- [ An Anon Engineer ]
We use 0-In CheckerWare. Very useful if used properly. Verifiers
would use them properly but they are a designer tool. It's hard to
get design teams to to the right thing to get maximum benefit.
- Kevin Jones of Rambus
Using 0-In CheckerWare
- [ An Anon Engineer ]
We use 0-In CheckerWare. Excellent return for limited effort, it found
about 25% of the bugs on a project that had people use it on a volunteer
basis. Adding assertions proved to be more efficeint than writing new
transactors or tests, it made our existing tests more effective.
- [ An Anon Engineer ]
PSL will be widely used.
- Greg Tumbush of Starkey Labs.
We have looked into PSL, and while using it in VHDL comments is odd,
we are considering it. I think in a couple of years. Ideally, it
would be fully integrated in the language rather than something
bolted on.
- Frank Vorstenbosch of Telecom Modus Ltd.
We did code SVA for a SoC design. My rating would be:
(1) SVA - lot of features, but yet to mature
(2) PSL - good old assertion language
(3) OVL - easy to use, but lags features.
It was hard getting the verification folks to use the assertions as a
part of their simulation.
- [ An Anon Engineer ]
Use OVL. Looking at PSL/SVA (been limited by tool support). They've
found a few nasty bugs.
- [ An Anon Engineer ]
We use both OVA (with Synopsys tools) and PSL (with the rest of the
world.) They have do's and don'ts:
PSL is quite expressive and reasonably standardized; unfortunately
it lacks of a good binding mechanism, so if you want to instantiate
several times the same library it's a mess (basically you have to
rely upon your own editing!!).
OVA allows you to do all you need, but is a bit less expressive
than PSL.
- [ An Anon Engineer ]
Assertion languages are an important part of any verification package.
I hope to convince folks in my company of that.
- George Gorman of LSI Logic
Not currently using.
- [ An Anon Engineer ]
Assertions are great to increase observality to ease debug and to
ensure proper reuse of an IP for integration. We mainly use PSL.
- Olivier Haller of STMicroelectronics
I do not use. But assertion within RTL is a good idea, will use it in
future projects.
- [ An Anon Engineer ]
Never used
- [ An Anon Engineer ]
No use.
- Michiel Vandenbroek of China Core Technology Ltd.
Not used
- Karthik Kandasamy of Wipro
No experience with assertion based languages.
- Juan Carlos Diaz of Agere Systems
Use OVL, OVA. Useful, but people use a very small subset of them.
- [ An Anon Engineer ]
We used the OVL library.
- Ba Nguyen of SonoSite, Inc.
We plan to use SVA, OVL is hard to use and not that big benefit.
- [ An Anon Engineer ]
OVL - Useful, actually help find bugs in designs quickly!
- Rajen Ramchandani of Mindspeed Technologies
PSL, some OVL. Very useful, but some engineers not convinced.
- [ An Anon Engineer ]
We don't use any of those, except a tiny bit of OVA. We have plenty
of assertions in our RTL, but the RTL designers write them all
themselves in Verilog. We occasionally use OVA as an interface
between the RTL the the Vera testbench.
- John Zook of Stargen
Playing with PSL - looks useful. OVL and OVA will die. OVL is weak
compared to the others. OVA is not widely supported.
- [ An Anon Engineer ]
Awesome Baby!!!!!!!!! Use PSL and they are very useful.
- [ An Anon Engineer ]
We have OVA available since it's part of Vera but I'm nervous about
investing the time and effort in learning it if the rest of the world
is using PSL or SVA in 2 years time.
- [ An Anon Engineer ]
We use non-temporal VHDL assertions everywhere in our code and we
find lots of bugs this way in simulation.
- Jay Brown of Top Layer Networks
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