( DVcon 04 Item 12 ) --------------------------------------------- [ 05/26/04 ]
Subject: Mentor Seamless, CoWare ConvergenSC, Annapolis CoreFire, Summit VCPU
NO, THANK YOU Other than the user response to graphical design entry tools
in an earlier part of this report, I've never seen an EDA tool category so
brutally rejected like HW/SW co-sim tools:
"Do you use HW/SW co-simulation like CoWare ConvergenSC
or Mentor Seamless?"
don't use : ############################################ 88%
Mentor Seamless : ### 7%
CoWare ConvergenSC : ## 3%
Annapolis CoreFire : # 1%
Summit VCPU : # 1%
Not only do the 88 percent rejection stats scream a loud "No, thank you", the
bulk of user comments reiterate this ill will, too. Ouch! (P.S. Swimming
against the tide, Lawrence Case of Motorola wrote an excellent first person
account of using CoWare N2C on a project in ESNUG 428 #8.)
We tried Seamless in the beginning. Very good tool! However, waited
6 months for Mentor and ARC to come up with the behavior model for the
ARCTan4 processor core, but no luck. We definitely would have saved
3-4 months in HW/SW integration had we received the required models.
Again, Seamless is a good tool but lacks support in terms of
availability of behavior models. Disappointing!
- Inder Singh of iVivity, Inc.
No. Used them in the past. HW team thought it was a good idea. SW team
regarded the simulator as too slow to be useful.
- Terry Doherty of Emulex Corporation
We used Mentor Seamless on a project a couple of years ago and it was
horribly slow. It may be better now, but we have moved on. We are
currently using a proprietary co-simulator that comes with our
RISC CPU IP and uses the FLI interface to Modelsim. It's working
quite well.
- [ An Anon Engineer ]
We don't use them. I've used Seamless in the past, and saw the value of
the tool. However, for the firmware guys, developing with it was REALLY
slow compared to the FPGA devel environment they were used to.
- John Ford of SolarFlare Communications
We used to use Seamless. There's no need now that we have Palladium.
- Carl Harvey of Cirrus Logic
We've tested Seamless but no one is screaming for it.
- [ An Anon Engineer ]
We don't use that either. Mentor Seamless looks interesting but we
don't really run real software on the RTL now so it doesn't really
fit in our flow.
- Laurent Claudel of Wavecom
No need for them.
- Michiel Vandenbroek of China Core Technology Ltd.
We used Seamless for HW/SW co-sim but it took a lot of time to bring up.
It wasn't really used well due simulation performance was too slow and
simulation model doens't have high level abstraction. Good concept, but
it requires cross functional of HW/SW commitment to make it happen.
- Hsing Hsieh of Hitachi
Have used Seamless, but doesn't seem to give any real advantages over
building in-house under SystemC/SCV. Unlikely to continue using
Seamless for current/future projects -- unless they can come up with
some compelling reason!
- Fraser Dallas of Motorola GSG (Scotland)
I have used Seamless with some success. It was hard to get the firmware
guys to wade into the water because they wanted "full speed". We did
have some success, though, until the project got axed.
- [ An Anon Engineer ]
Yes, we use Seamless. It was very good, got SW involved early and
accelerated chip bring-up.
- Brad Hollister of NetSilicon, Inc.
Seamless is good for limited HW/SW co-sim but clumsy to integrate into
your sim environment.
- [ An Anon Engineer ]
We have CoWare's ConvergenSC.
- Gao Peng of Tongji University, China
Have used Mentor Seamless in the past. The key idea is to get the SW
team started sooner, and maybe discover a few (or many) hardware bugs as
a by-product. While the various optimizations in Seamless help in
speeding up co-sim, your mileage may vary depending on your specific
application. Definitely useful.
- Ambar Sarkar of Paradigm Works
We've used Seamless. It's OK.
- [ An Anon Engineer ]
We have used VCPU from Summit.
- Tom Paulson of QLogic Corp.
The quality of the ISS models is a crucial issue. We had experiences
where we spent more time on debugging the ISS model (about 30 faults)
and it was especially annoying to know that this work did not improve
the quality of our core. So with respect to the chip verification
itself, the ISS debug was a complete waist of time.
- Andreas Dieckmann of Siemens AG
I've used Seamless. It was slow, but it did help us find bugs pre-
silicon. Main problem we found was that if your on-chip memories are
not directly addressable by the processor, then there's no optimization
that Seamless can do to speed things up.
- Christine Gerveshi of Agere Systems
Not yet. We might shoot next year for CoWare ConvergenceSC with Axis.
We will see...
- Remi Francard of STmicroelectronics
No, but we are looking into some of the PCI/Modelsim based offerings.
We do have a couple copies of Annapolis CoreFire.
- [ An Anon Engineer ]
CoWare ConvergenSC: its simulator has to be faster than OSCI.
- Benoit Clement of STMicroelectronics
We use ad-hoc solution for HW/SW co-simulation, designed in-house.
- Javier Jimenez of DS2 Spain
We use our own C/FLI/Socket interface to run co-simulation which can
get lots of driver/firmware stuff developped and debugged.
- Alex Chao of Topspin Communications
Looked at Seamless. Our CPU wasn't properly supported.
- [ An Anon Engineer ]
No
- Greg Arena of Intel Corp.
No.
- Winston Worrell of Microsoft
No
- [ An Anon Engineer ]
We've found it's just so much easier to roll our own co-sim environment.
- [ An Anon Engineer ]
Our designs are virtually all SoC based, and include an embedded
processor of some sort. We do not use any specific HW/SW co-simulation
products, but rely instead on RTL and gate-level simulation of the
system -- including software.
This can be fairly slow, and so to increase the software coverage we
also use FPGA based prototypes. If any issue is found by running
software on an FPGA board, then this situation can be simulated
fairly quickly, and hopefully resolved.
Any critical sections of software (such as boot up of our RTOS) will
still be simulated to make sure they function correctly. This approach
works well for us, and we generally have our RTOS up and running within
a day of getting silicon back.
- [ An Anon Engineer ]
Not hardware/software. We do use the Matlab simulation capability in
Aldec's tools however.
- Ray Andraka of Andraka Consulting
We do not do HW/SW co-sim.
- Samuel Russell of Ceva, Inc.
No. We have considered using Seamless in the past, but we currently
don't have a project requiring these abilities. If we did, we
definitely believe that co-simulation and/or HW emulation would
be useful.
- Jim Lear of Legerity
We've tried using co-sims in the past, but they never really took off.
This could have worked for us, but there is too much of a divide between
our hardware and software groups to make this successful.
- Jonathan Craft of McData Corp.
Do not use.
- [ An Anon Engineer ]
Not used. Should be to explore your software on your design before
your customer does.
- [ An Anon Engineer ]
No. (We have a homegrown solution)
- [ An Anon Engineer ]
NO
- [ An Anon Engineer ]
No
- Tomoo Taguchi of Hewlett-Packard
No.
- Don Monroe of Enterasys Networks
No HW/SW co-simulation used.
- [ An Anon Engineer ]
We use our own in-house co-sim interface via PLI and SystemC with Verilog.
- Chandresh Patel of Ciena Corp.
Not that I am aware of.
- Jerry Roletter of ATI
Not yet, but may consider in future for SystemC. Nice GUI for debug.
Not sure. Need to evalute.
- [ An Anon Engineer ]
No, we send the FPGA board down to the 4th floor. The big effort is
getting the software department to do something meaningful before
tapeout.
- Mark Andrews of EFI, Inc.
No.
- [ An Anon Engineer ]
Nope...
- Sandro Pintz of Precision IO, Inc.
No experience.
- Nathan Dohm of StarGen, Inc.
I don't use any of them. I used to use Mentor Seamless. It was OK.
- Jithendra Madala of QuickSilver Technology
No - use C with Verilog PLI. We can do a lot of things that way, that
CoWare and Mentor Seamless can't do, and they're a lot more expensive.
- [ An Anon Engineer ]
Nope.
- [ An Anon Engineer ]
They are out of our realm.
- Bill Dittenhofer of Starkey
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