( DVcon 04 Item 7 ) ---------------------------------------------- [ 05/26/04 ]
Subject: TransEDA, Atrenta Spyglass, Novas Debussy, Verisity SureCov
THE HOME COURT ADVANTAGE Life's kind of rough in the HDL simulator add-on
market. For example, in the "code coverage" business, outside 3rd party
tools get only 25% of the total available market. A whopping 75% of code
coverage goes to the built-in tools already in the simulator.
Cadence built-in (HDLScore) : ###################### 22%
Mentor MTI built-in coverage : ####################### 23%
Synopsys built-in coverage : ##################### 21%
Aldec built-in coverage : ######### 9%
TransEDA coverage : ################# 17%
Verisity SureCov : ######## 8%
Life's a little easier for the 3rd party folk in the "lint" niche. They get
32% of the business and the built-ins get 60%. But watch out! The non-
traditional freaks of the lint world (0-in, RealIntent, & Verplex) are
skimming off 11% of that market, too.
Cadence built-in (HAL) : ################# 17%
Mentor MTI built-in lint : ############## 14%
Synopsys built-in lint : #### 4%
Synopsys Leda : ########### 11%
Synopsys Verilint : ##### 5%
Aldec built-in lint : ######### 9%
Atrenta Spyglass : ############## 14%
Novas nLint : ######### 9%
Verisity SureLint : #### 4%
TransEDA vnlint : #### 4%
Veritools HDLlint : # 1%
0-in Checklist lint : ##### 5%
RealIntent lint : ## 2%
Verplex lint : #### 4%
It's only in the "debug" category do the 3rd party tools have a fair share of
the pie. Here 3rd party (Novas really) gets 48% vs. built-in's 52%.
Cadence built-in (SimVision) : ################### 19%
Cadence Signalscan : # 1%
Mentor MTI built-in debug : ################# 17%
Synopsys built-in (Virsim) : ####### 7%
Aldec built-in debug : ######## 8%
Novas Debussy : ########################### 27%
Novas Verdi : ######### 9%
Novas Nschema : ####### 7%
Novas nTrace : # 1%
Novas nWave : # 1%
Veritools UnderTow : ##### 4%
But to be intellectually honest, in each category (coverage, lint, debug)
the built-ins either dominated or at least held a simple majority. (75%,
60%, 52%) Why buy the cow when you can get the milk for free?
For "linting" (I call it design checking) we use 0-in Checklist which
only checks 25 really cricital design issues like arithmetic overflow
index out of range, combinational feedback loops, clock domain crossing.
We tried Atrenta SpyGlass for a year and eventually concluded that
Spyglass was TOO configurable - it literally has 10s of thousands of
rules that you have to figure out if you need to check for. Atrenta
did not supply any "preconfigured" rule sets that produced a reasonable
amount to violations to check. Having gone through this experience,
I decided that a tool that only does what I care about - check for
coding problems that will cause problems down stream (mainly synthesis,
but also simulation and equivalency checking) and not ticky-tacky
stuff like whether the code was indented correctly - was what we needed.
If we had a few spare man months of engineering resources, Spyglass would
have been great to create a very customized checking environment, but
given our schedules and resource constraints, it made more sense to pick
a tool that just checked the really important stuff.
The other nice thing about Checklist is that it will generate assertions
that can be used with other 0-in tools that will fire if an arithmetic
overflow or index out of range condition occurs in your simulations or
formal checking.
- Tomoo Taguchi of Hewlett-Packard
We are still quite small and only want to spend money on simulator
licenses, so we use MTI's built-in coverage. It's not perfect but
acceptable.
- Alex Chao of Topspin Communications
We use 0-in. Their Checklist tool is a pseudo-linter and catches some
bugs that other linters miss. Very easy to use. Also comes with a
Clock Domain checker. Can anyone compare this to SpyGlass?
Assertions are excellent for verifying block interfaces. Especially
standard interfaces, for which verification IP is available. They are
also good for standard blocks like fifos, arbiters, req-ack interfaces,
etc. But the nastiest bugs in your design come from nonstandard blocks
and interfaces. Assertions don't help there. Use assertions for the
low-hanging fruit, but don't put too much faith in them.
- [ An Anon Engineer ]
We have also used the 0-in Checklist tool to perform basic integrity
checks and to carefully review our clock domain crossings. They
cover most common ways that clock domains can fail and give us many
reports of possible violations that we then carefully review.
- [ An Anon Engineer ]
We use 0-in's Checklist for linting. It has proven to be very useful;
especially in the area of clock domain crossings and for a quality check
of 3rd party IP.
- Mike Peters of Digeo, Inc.
We use Leda. It is very simple to run against our own customized
policies. Low overhead way of identifying a large variety of problems
quickly. Can also be customized to add checks to detect previously
experienced problems... a way to avoid repeating the same problem.
Also streamlines code reviews.
- Scott Runner of Qualcomm
Leda is Synopsys' replacement for Verilint. It doesn't feel as mature
as the other Synopsys tools, with an odd installation structure and
usage model. But Leda seems very flexible, with a long list of
built-in rules that can be selected/deselected. Also, Leda supports
the newer dialects of Verilog, whereas Verilint doesn't.
As an aside, Formality is a great Linter! It doesn't spew tons of
inconsequential warnings, like DC HDL Compiler or Verilint do. But,
when it does complain, it's almost always something you need to
seriously consider in your RTL.
Debussy is great for generating and traversing schematics! This isn't
the most common use of the tool, but it's great for visualizing design
hierarchy or cones of logic for some huge netlist that's been tossed
your way.
- John Busco of Nvidia
We bought Vnavigator, but no one liked it. Currently our policy is to
use the built-in coverage capability of the simulator. We use Debussy
and nSchema and love that tool. But their price is high.
- [ An Anon Engineer ]
Surelint - looking for a replacement.
SureCov.
MTI built in coverage is still immature.
Leda, HAL, Spyglass - Could be useful if free.
Debussy/nSchema - good.
- Winston Worrell of Microsoft
We use TransEDA Verification Navigator (VHDLCover?). It is fairly
simple to set up and use, and integrates with Modelsim. I tried MTI's
code coverage several versions ago but at the time it was extremely
primitive. I know they've improved it since.
Novas came onsite a few months back and did a presentation about
Debussy -- there was considerable interest but I don't know what
came of it.
- Aviva Starkman of Northrop Grumman
I do not use linters very much. The most effective linter is the new
VHDL RTL reader in Formality.
- Umberto Rossi of STMicroelectronics
Formerly used TransEDA. For some reason their support fell through.
We now use Mentor Modelsim's coverage tools.
- John Ford of SolarFlare Communications
LEDA yes, SpyGlass yes. HAL was not as mature as expected at the time
we tried it. Moreover HAL using NC compilation pretends to be sign off!
Effectively the first pass of HAL is the NC compiler. The NC compiler
elaboration phase is not serious enough to be sign off. It would take
libraries or components that have been compiled without cross check on
port size and missing information (outputs missing for instance).
- Remi Francard of ST Microelectronics
SimVision's capability to link the transactions is proving to be a big
advantage. I need it to analyze the split transactions, which is only
possible by linking transactions. The TxE tool inside SimVision is very
slow, but other than this TxE is a very powerful tool. More examples
need to be displayed to uncover its true potential.
- Sudhanshu Chadha of STmicroelectronics
We use Undertow for years. Verdi is very nice for high-level-debugging.
- Stefan Rohrer of Micronas GmbH
We have no coverage tool in use. We use is the built-in linter from
both RealIntent and Verplex.
- Yuval Itkin of Metalink Broadband, Ltd.
My experiences have been primarily with SimVision. I'll begin by saying
that the NC-Sim family has improved greatly over the last several months.
I first used the NC line in Q3 of 2003. There were numerous bugs
that caused various levels of crashes. Most of these appear to have been
fixed. SimVision now only crashes a few times a week for me. We're
using it to verify a medium size design (~2,000,000 logic gates or
so). We are using Verilog with a few PLI components. No SystemC, no
assertions, no HVL.
The failures I see typically happen after I've closed and opened several
different databases for post-processing without closing/re-invoking the
tool. I also see more frequent crashes when viewing code and schematics
in addition to waves. In the last few months, in particular, I've
noticed that the tool crashes more gracefully than in late 2003
versions. Often I'm able to save the bug report, or opt out of doing so
sucessfully. Previously that was not typically the case.
The most persistant problems I see now are the same minor GUI quirks
that have been there since 2003. Often when using the MouseButton-1,
MouseButton-2, MouseButton-3 sequence to zoom in on a chunk of waves,
the tool wants to pan the waves left or right whenever the mouse goes
left or right of the waveform pane. It does this until you do the
Ctl-MouseDrag zoom to get it to turn loose. Pretty annoying, but not too
bad. Another bug is that sometimes when trying to drag-n-drop, either
between windows, or w/in the same window, you can't drop what you're
dragging. Rather, you need to click to place the items.
By far the most problematic bug, however, is the instability of the
GUI. As I state above, it's come a long way. It's not there yet,
though. A few crashes a week is the level of stability I expect from a
MicroSoft product. And easily the best thing about the tool is how
intuitive most things are. I've given up trying to live with Debussy for
anything but gates, in favor of NC. This is due entirely to the
intuitive nature of the tool.
- [ An Anon Engineer ]
We use HAL, it helps. We will make some use of Cadence's built-in code
coverage but base most of our metrics on functional coverage. We don't
use any bolt-on GUIs for viewing or entry.
- Pete Cumming of Icera Semiconductor
We use TransEDA VNCover for code coverage. It gets the job done and
that is why we have not looked into anything else recently.
- Karl Kaiser of EcoLogic GmbH
Although our group has a license to use Debussy, I don't use it. I
think it's a waste of time. I prefer more traditional debug techniques.
For coverage, we use VCS' built-in coverage combined with Specman's
functional coverage.
- Greg Arena of Intel Corp.
Still using Surelint as a linter but in the market for a replacement.
VCS built-in code coverage is good enough for us. Everyone loves
Debussy/nSchema.
- [ An Anon Engineer ]
Third-party coverage tools are hard to get working, so I prefer the
built-in tools. Synopsys VCS coverage seemed to work well, but we
switched from VCS to NC-Sim. Cadence had NC-COV which was easy to get
set up, but had awful performance and was buggy. They bought HDLScore
and were in the process of integrating it with NC-Sim last I heard, but
haven't had the chance to use it yet. I hope it's easy to use. We have
used Verilint for linting, but I think our company is investigating
alternatives.
- Ty Gallander of Conexant
I've used both SpyGlass and Novas Software nLint. They're both
programmable so you can add some of your coding guidelines to be checked
automatically along with all the built-in checks. Spyglass tries to
catch some of the problems you may see in the downstream tools like DFT,
but it didn't catch any we encountered.
I like the early warning system, but get really tired of sorting through
all the unnecessary warnings. I know you can turn individual cases off
but you still get lots of warnings to go through. I think they're a bit
too high priced for the minimal value add.
Evaluated VCS coverage about a year or so ago while using HDLScore
(Cadence now). Failed our first test case. Never looked at it again.
We presently use SureCov here. We found both false positives and false
negatives. Not too reassuring. We're switching to Cadence. I've used
it for more than 10 years (as HDLScore) and trust it. Did a quick test
between SureCov and HDLScore on a false positive coverage we were getting
and sure enough HDLScore said (correctly) it wasn't covered.
- [ An Anon Engineer ]
Synopsys VCM (Coverage Monitor): We use it extensively but support is
poor and the tool is buggy. This begs the question how much Synopsys
is investing in it. Other tools we use: nLint, SpyGlass, Debussy
- [ An Anon Engineer ]
We're using Veristy Surecov for the first time. We've used the Mentor
and Cadence built-in tools and they're fine for what they do. I love
Debussy, can't say enough good things about it. Vastly superior
to Undertow in terms of capabilities.
- Christine Gerveshi of Agere Systems
Using VCS built-in coverage tool. Used Spyglass in earlier company
for linting.
- Ajit Madhekar of ControlNet India Pvt Ltd.
We currently are using the free Cadence code coverage tool. It's worked
well for us. I've not tried SureCov yet. I like HAL. I use this to
find ways to code better. We are currently evaluating Leda and SpyGlass.
I think we will start using one of them.
Most of us are using SimVision (the old SignalScan viewer). We have an
engineer who still uses Undertow. This tool can't handle are large
databases efficiently so is only used for some small module development.
- Maynard Hammond of Scientific Atlanta
Synopsys LEDA for linting. LEDA has a lot of problems, array of
instances, ANSI port list, and synchronous resets. It is disappointing
to know that Synopsys can handle it in DC but their linting tool cannot.
- [ An Anon Engineer ]
We used to use HDLScore. We have since switched to the "free" one in
VCS. We have seen a HUGE performance benefit from doing that. Out of
all the coverage metrics, we generally only use the most basic features,
line/state coverage. The other metrics are rarely looked at.
- Dan Steinberg of Integrated Device Technology
Novas Nlint and Synopsys Leda. Now use VCS, dont use others. Leda and
Nlint is useful.
- Luo Min of Northwestern Polytechnical University, China
TransEDA is our coverage tool of choice. It gives fairly good results,
though with a few anomalies from time to time. It's fairly good value
and does the job we want it to.
- [ An Anon Engineer ]
SimVision: Is best known (in my circles) as Cadence's waveform viewer.
It really is more than that, since it is also their GUI i/f for running
simulations and debugging your design. It has been around for years,
but they recently overhauled it, assimilating the guts of Signalscan
(which they acquired) into this new version. Our team, being very
command-line oriented in running simulations, really liked the Signalscan
waveform viewer, and stuck with it for as long as possible. Just now
starting to really use SimVision.
One suggestion maybe a more progressive look and feel. GUI is still
pretty "unix blocky", if that is even a real term.
- Mike Bly of World Wide Packets, Inc.
TransEDA is used, but expensive. Selection of such tools seems more of a
design team decision, so no company-wide shared opinion I guess.
- Frank Ghenassia of STMicroelectronics
Spyglass - even though support intensive. It had serious noise/clutter
issues out-of-the-box. We use the built-in VCS coverage and Debussy.
- Tom Heynemann of Hewlett-Packard
We use VCS built-in line coverage and Leda. Both are fine. Not familiar
with the other tools listed.
- Brad Hollister of NetSilicon, Inc.
We use Spyglass. We also use NovaRTL a little bit. We are not satisfied
with the built-in coverage of Mentor MTI. Not sure about other tools.
- Mohammed Zaman of Analog Devices, Inc.
TransEDA vnCheck
- [ An Anon Engineer ]
SpyGlass for linting, Covermeter for coverage. I have not been really
happy with any solution. Linting needs good direction, which isn't too
bad. Coverage takes way to much analysis after, and can still miss
too much. Not really any better than the old "toggle" coverage.
- [ An Anon Engineer ]
Code coverage is mandatory and we use TransEDA. They also have a nice
automatic FSM coverage solution. Modelsim coverage looks also to match
with our requirements. So for performance reasons we might switch to
Modelsim.
Debussy is useful occasionally for design explorance.
We do not use static checkers/lint tools.
- Thomas Langschwert of Infineon
Have used Verisity Surelint, Novas nLint, Cadence HAL. Surelint is
clearly the best. Very good GUI for reporting/browsing warnings errors.
Easy to use; easy to filter warnings. Excellent extraction of FSMs and
race conditions. Biggest drawbacks: 1) Verisity no longer supports it;
2) no clock-domain analyzer; 3) no Verilog 2000 support.
Novas nLint is OK. Most complete error/warning reporting. Relatively
easy to use, but GUI is overly complicated. Links to nSchema/nTrace
are unnecessary and a shameless attempt to sell more software. Clock
domain analyzer is good. Has anyone compared this to SpyGlass?
Cadence HAL isn't competitive. No help in analyzing FSMs, race
conditions, or clock domains. Having to compile the design first is
a big minus -- all the other tools simply take a source file list.
DeBussy rocks the free world. SimVision and the Synopsys waveform
viewer don't even come close.
- [ An Anon Engineer ]
We are starting to use Leda for linting. We also use Modelsim's code
coverage tools - the new release has additional features like conditional
and expression coverage.
- [ An Anon Engineer ]
SpyGlass looks very good, and we'll likely use it next design. Last
time we evaluated Leda (early-2003) we were NOT impressed.
- Mark Curry of Texas Instruments
Aldec Debuger and Code Coverage. Very pleased with the tools provided.
- Reza Shirali of Orbital Sciences Corp.
We have used TransEDA for code coverage (VHDL) and found it quite good.
Evaluated some of the linter tools (Leda, Spyglass). The evaluation was
not extensive, but found the after running VHDL through the syntax
checker in simulation and synthesis they didn't catch much that was
important. And without a compelling reason we didn't thing designer
would spend time reading the many message they generated.
- [ An Anon Engineer ]
@HDL linter, built-in Synopsys coverage (which sucks)
- [ An Anon Engineer ]
Was using Verisity SureCov. Will probably be switching the NC-Verilog's
built-in due to cost. Two most important things about coverage:
1. show you which parts of the design are NOT covered
2. must remember that just because you've executed
the line, you may not have tested it. This is
especially true in timing dependant areas such
as clock-domain synchronizing fifo's and high-level
of complexity interfaces (PCI-X)
Don't see the bang-for-the-buck out of Debussy, etc.
- [ An Anon Engineer ]
We use Modelsim's code coverage capabilities. It is exceedingly easy to
implement and is sufficient for our needs. We wrote a couple post
processing scripts to present the data in the format that we like.
We have written our own homebrew lint tool that checks code against our
style-guide as well as for many flaws in code.
- Jay Adams of Marconi Corp.
Cadence's HAL tool and Verplex tool for linting and other checks.
HAL is ok but not too useful; just informative. I like Verplex better.
TransEDA Verification Navigator for code coverage.
NC-Sim and Modelsim for functional coverage and code coverage (Modelsim).
We're still deciding on a formal assertion checking tool.
- Carl Harvey of Cirrus Logic
Spyglass is a waste of time.
Verdi is useful.
- [ An Anon Engineer ]
I have used the coverage tools in MTI (a while ago) and SureCov (not
quite as long ago). In both cases the information was useful in pointing
out places where we had holes in our coverage, but in both cases we used
scan to get fault coverage so we waved our hands and counted on magic
incantations to appease the Testing Gods. I have not used SpyGlass,
though others around here have. I have used DeBussy to help wade into a
large, largely uncommented, piece of VHDL that someone else wrote. I
also linked it to the simulation and used it to trace unknowns and some
other "unexpected" behavior and found it quite useful.
- [ An Anon Engineer ]
We have always used TransEDA Vnavigator for code coverage. It is a well
thought out tool. We may investigate VCS built-in coverage again but
last time we looked at it about 2 years ago, it was crap!
We use Spyglass from Atrenta. It is useful. Generates a lot of noise
but is excellent for handling the tricky clock domain crossings. I have
recently evaluated LEDA and I would rate it as Beta quality compared
to Spyglass.
- Samuel Russell of Ceva, Inc.
We use HAL. It's OK (but not more than that).
- [ An Anon Engineer ]
Graphical design entry tool: Summit Visual Elite
Linter tool: Cadence HAL
Coverage tool: TransEDA Vnavigator
Debug tool: Cadence NC built-in
The coverage tool allows us to improve our tests pool. We really would
like to use Novas DeBussy for debug but in this time of cost reduction
it has always been seen as non-prioritary by our management.
- [ An Anon Engineer ]
Lint: Nlint, Spyglass, Verplex RTL-to-RTL.
Leda and HAL are a waste of (setup) time
Coverage: project specific, but SureCov, TransEDA
Debug: DeBussy and SimVision
- [ An Anon Engineer ]
I do not view coverage as a stand-alone tool any more. Coverage is a
feature built in to the major simulators.
- Jonah Probell of Ultra Data Corp.
We're using built in Cadence for coverage. Have to learn it next week.
- Ross Smith of Theseus Research
Veritools Undertow for waveform only.
Cadence SimVision for interactive debug.
Novas Verdi for design & IP browsing and behavioural analysis.
- [ An Anon Engineer ]
We've used TransEDA for coverage on the past 4-5 ASICs we've done, and
recently attempted to make the switch to VCS's built-in coverage. The
built-in tools are a helluva lot faster, of course, but we've found
them to be innaccurate and very difficult to use, especially when trying
to merge results from multiple tests. The TransEDA GUI is very slick,
except for their marketing bubbles that remind us of the fact that we
don't own every single part of their toolflow. Hard to generate text
reports, but nice in most other respects. We'll probably stick with them
in the near future until VCS can get its act together.
- Jonathan Craft of McData Corp.
Code coverage tools we use: TransEDA on the Cadence side, built-in
coverage on the Synopsys VCS side. We pay more attention to
functional/stimulus coverage then to code coverage.
40% of the company uses Debussy, including Verdi.
- [ An Anon Engineer ]
We use Spyglass for RTL. We are looking at the Specman linter for the
testbench. Debussy and Verdi are both productivity enhancement debug
tools for engineers that do not know the RTL. We use them.
- Robert Young of Intel
We're using Cadence HAL and HDLScore. We were using Surelint and
SureCov and were very happy we them except that Surelint is now dead
(no development anymore) and will never support Verilog2001. HAL was
very limited when we first tried it more than 2 years ago but been
drastically improved and is now very good. It still saves a lot of
time, especially in Verilog, to lint the code before moving forward
in the design flow. SureCov is well behind also for Verilog2001 and
since HDLScore comes for free and does what we need ...
- Laurent Claudel of Wavecom
Nova for lint, HDLscore for code coverage. Verisity SureCov is buggy;
does not deal with glitches thus reports a too high coverage. Cadence
built-in coverage is good. Mentor is bad; way behind in functionality.
Leda is buggy and very slow. SpyGlass is nice but advanced features
cost a lot of money. Novas is a waste of time.
- Boaz Ben-Nun of Starcore DSP
We use TransEDA VN-Cover and Modelsim's built-in coverage tools.
Currently trying to determine if TransEDA coverage provides any
additional benefit above Modelsim's coverage.
- [ An Anon Engineer ]
Use TransEDA, and it is still far ahead of built-in vendor offerings in
terms of robustness and feature set. SureCov is still only for Verilog,
so is a non-starter for us. Debussy is being increasingly used, and is
good for design debug.
- [ An Anon Engineer ]
We did not use any linter and definitely felt the pain and need for it
during verification. SureCov is O.K., has some certain problems.
Due to lack of technical support on SureCov we are switching to
Cadence's NC-Verilog code coverage on the next project.
- Inder Singh of iVivity, Inc.
We use Novas nLint, Cadence SimVision. Previously we used TransEDA code
coverage, but the built in Cadence coverage tools are looking promising
for the time frame that we will need it.
- [ An Anon Engineer ]
Novas nLint for linter, Novas Debussy for debug, VCS and Modelsim
built-in coverage for code coverage.
- Gao Peng of Tongji University, China
We use the VCS coverage tools, with Novas nLint for linting. And we're
using Debussy for debug.
- [ An Anon Engineer ]
Lint tools are nice, but can be a pain in the backside, in particular
when the pointy haired boss and or QA people are demanding it passes
with no errors or warnings. Used Atrenta Spyglass, which was only
so-so... We now invest more time into teaching the engineers to write
good code rather than chasing problems later. The 'lint' flow now
simply means the code compiles with no errors and minimal warnings in
the various tools, e.g. NC-Verilog and dc_shell, and I usually
personally eyeball the code for style and readability for our new
engineers, until they 'get it'.
I've used various code coverage tools, e.g. CoverMeter, VeriCov, etc.
Currently we use HDLScore. Built-in or not is not a big issue, unless
you pay extra for it, in which case I wouldn't want it. Also, RTL
coverage is nice but not nearly enough, so we supplement it with
in-house netlist coverage tools and a big dose of functional/spec
coverage analysis. A project in another department has been caught
with a silicon bug despite 100% VeriCov coverage. :)
- Michiel Vandenbroek of China Core Technology Ltd.
Economics is forcing the usage of built-in coverage and Virsim tools
packaged with VCS. May use Leda.
- Chandresh Patel of Ciena Corp.
Built-in code coverage is easy, so we use that on most projects. I
personally use VCS Virsim for debug, but I know others around me use
DeBussy.
- George Gorman of LSI Logic
MTI is much stricter than VCS. You need a linter no matter what.
DeBussy/Verdi/nSchema doesn't cope with all legal constructs.
- [ An Anon Engineer ]
Lint: NC-HAL, Verplex
Debug: SimVision, DeBussy
Coverage: NC HDLScore
I think the built-in code coverage tools are sufficient. TransEDA has
very good tools but overkill for finding/traversing paths not hit by
tests. NC-HAL is OK but could be better. Wished it supported cross
clock domains.
- [ An Anon Engineer ]
Code coverage is not a waste of time but money. I'll take them for
free!! If I have it, I'll use them. If not I will not buy them.
We'll probably just use the embedded debugger -- SimVision or
Virsim. (ouch!!)
- Sandro Pintz of Precision IO, Inc.
We haven't used much of coverage, but I hope to in the future. I used
SureCov before and really liked it. It is only for Verilog though. We
are going to try and use the built-in version in Cadence. One of them
is lame and the one that they bought (HDLScore?) seems to be decent and
does both Verilog and VHDL. We'll probably try that because it is free.
Some people use Undertow where I am and some have used DeBussy and
really liked it.
- Jerry Roletter of ATI
We lint by making the code pass through VCS, dc_shell and Novas Debussy.
We use the code coverage in VCS, which we owned before it was absorbed
by the EDA equivalent of the Borg cube. No Leda nor Atrenta.
We love Debussy, we own one seat of Nschema, but virtually never use.
Verdi is just too expensive to justify the cost.
- Mark Andrews of EFI, Inc.
We use TransEDA vnlint as a linter and checker.
- Brien Anderson of Siemens Medical
We use HDLLINT from Everest; it serves the RTL designer's needs for the
most part, although it would be nice to catch DFT violations and other
things that screw up DC earlier, we don't have a good flow for that yet
and not all the checks are in the lint tool.
I looked at Leda when it first came out -- it seemed like it could do
some cool stuff, but the administration overhead looked like a problem
for us; someone on the project would have to spend serious amounts of
time maintaining & running it. It did not seem suited for RTL designers
to be running on their code dozens of times per day. The price was also
very high for a lint tool.
We have been using Novas Debussy for 4+ years on our projects, I spend
half my life working in it. It's great, I'd be upset if I had to use any
other graphical debugger. It had some stability problems when we first
started using it, but it's pretty solid now. It seemed kind of expensive
at first, but it turned out to be one of our best "bang for the buck" CAD
tool purchases.
- Nathan Dohm of StarGen, Inc.
The built-in coverage tool with Synopsys VCS. Useful.
- Ram Sunder of Specular Networks
None for linter, Modelsim and Debussy for debug, HDL Navigator for code
coverage. Past history of comparision TransEDA vs. Mentor MTI had
shown TransEDA have more in depth coverage analysis, but MTI 5.8 have
improved since, more benchmark is required.
Synopsys LEDA was used on VHDL design had a lot of issues. There wasn't
a good impression on LEDA; we were doing quality assurance for Synopsys.
It was waste of time because ASIC vendor already had a pre-layout tool
that does more and most design problems had already been flushed out.
Novas's DeBussy had been used primary on gate level debugging. However,
comparing Debussy to Undertow, Undertow seems to have better performance.
- Hsing Hsieh of Hitachi
We have used the coverage in TransEDA, seems to be adequate if the design
isn't too big. We dont use a linter. We used the display that comes
with ModelSim, that has been adequate.
- Bill Dittenhofer of Starkey
Leda for linting and Modelsim for coverage.
- Greg Schmidt of General Dynamics
Mentor MTI for coverage and debug. TransEDA is still superior though
and we run all final checks through TransEDA. Synopsys Leda for lint
checker although it's a struggle to get the RTL designers to use it
consistently.
- [ An Anon Engineer ]
Don't use a lint tool although current projects are FPGA only. Would
definitely use one (LEDA) for ASIC development.
- Don Monroe of Enterasys Networks
We use nLint (from Novas). For coverage we use built-in VCS
(ex-CoverMeter). Waves, we still use DAI (Cadence, now) Signalscan but
also have Debussy licenses. Signalscan is dead/dying as standalone,
which is very sad since it was good and cheap.
- [ An Anon Engineer ]
For code coverage we are using Cadence ICT which is part of the simulator
and it is working well. No need of SureCov or TransEda as the built in
coverage tools provide the same/better features than standalone once.
Lint is useful and we are using Cadence HAL. For debugging we were using
DeBussy but we are moving to Cadence SimVision which is looking real
good now with lot of features.
- Jithendra Madala of QuickSilver Technology
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