( DVcon 04 Item 2 ) ---------------------------------------------- [ 05/26/04 ]
Subject: Modelsim, VCS, NC-SIM, Aldec, Icarus, SynaptiCAD, Wellspring
CADENCE IS KING When you look at the Verilog/mixed/VHDL data below, it's
real easy to brush this survey off as being just a North American centric
thing. Verilog dominating, weak VHDL, strong mixed. The assumption is
that VHDL is much, much stronger in Europe -- but that's simply not true.
When you're reading the actual user comments in each section you'll see
they're from all over, not just North America. I'm talking Spain, Italy,
Germany, India, mainland China, Japan, Sweden, Scotland, Israel, Belgium.
"Does your project do mixed Verilog/VHDL simulations?"
Verilog only : ######################### 49%
mixed : ####################### 45%
VHDL only : ### 6%
"Whose Verilog or VHDL simulator(s) do you currenty use?"
Mentor Modeltech : ######################################### 41%
Synopsys VCS : ################################## 34%
Cadence NC-Verilog : ####################### 23%
Cadence NC-SIM : ###################### 22%
Cadence Verilog-XL : ##### 5%
Cadence NC-VHDL : # 1%
Aldec : ####### 7%
Icarus : # 1%
SynaptiCAD : # 1%
Wellspring : # 1%
Silos-III : # 1%
Yup, that totals to 137%! This is because it's extremely common for chip
designers to use more than one company's HDL simulator. The most common
user statement is "...Modelsim and...". Yea, Modeltech's looking good here
with that leading 41% user share, but don't be fooled. Cadence is still
king in the HDL sim biz. Add up all of those individual Cadence simulators
and you'll see that they're at 23% + 22% + 5% + 1% = 51% of the user sites!
We are currently using a mixture of NC-Verilog and ModelSim, however
this is likely to move to simply NC-Verilog in the very near future
as we are seeing a speed-up of around 1.7x in favour of NC.
In the past we have used NC-Sim for mixed HDL simulation as we were
using some 3rd party IP that was in VHDL and all our internal design
work is in Verilog.
- Fraser Dallas of Motorola GSG (Scotland)
Modelsim and VCS. Mixed: Modelsim... starting to use VCS-MX
- Scott Runner of Qualcomm
We use NC-VHDL and Modelsim. Mixed HDL done with Modelsim because our
cores are available in both VHDL/Verilog but some older testbenches are
VHDL only.
- Thomas Langschwert of Infineon
Currently we are using Modelsim and SynaptiCAD Verilogger for our sims.
- Mohammad Bhaiji of Ontic Technologies, Inc.
Modelsim and Icarus Verilog. Do mainly Verilog. VHDL on customer
request basis. No mixed Verilog/VHDL simulations.
Icarus Verilog is an Open Source Verilog simulator. We use it for block
level simulations, but have also used it internally for netlist
simulations. It scales OK and is available on Linux, FreeBSD etc.
Icarus has been a great little tool for block level qualifications. I
like the licence-free ability to run as many instances as needed. It
lets me do lots of block level testing (in parallel) before integration
simulations with Modelsim as a final check.
- Joachim Strombergson of InformAsic AB
We use Wellspring Veriwell for most of our Verilog simulation. Some
people here also use Icarus Verilog. Everything that we simulate
is written in Verilog '95.
- Jonah Probell of Ultra Data Corp.
We've been a Cadence (Verilog-XL/NC-Sim) team for 3-4 chip generations
(5-6 years). For last two, we've been mixed Verilog/VHDL, and see a
mixed environment for just about all future designs. For next design,
however, we're looking at System Verilog which pushes things in favor
of VCS and MTI. MTI seems to have better (more mature) mixed language
support than VCS.
- Mark Curry of Texas Instruments
Cadence, we are using NC-Sim version 5.1, on Linux machine. We work
only with Verilog.
- Dorit Moshe of IBM Israel
Our group currently uses VCS 6.1/6.2 and Verilog-XL 3.4. We do not do
any VHDL work.
- Greg Arena of Intel Corp.
Modelsim 5.8b, VHDL only
- Rainer Mueller of Oasis Silicon Systems
Mentor Modelsim. Our entire design flow is conducted in VHDL, just the
final netlist taped out is Verilog. We do mixed Verilog/VHDL sim on
that final netlist (as well as post-layout drops from our ASIC foundry).
In those cases, the netlist is Verilog but the testbench is VHDL.
- Aviva Starkman of Northrop Grumman
Cadence NC-Verilog, currently digital Verilog only.
- Pete Cumming of Icera Semiconductor
We use Cadence NC-Sim mixed Verilog/VHDL simulator. Our code is mostly
written in Verilog but we use some 3rd party VHDL IP.
- Karl Kaiser of EcoLogic GmbH
VCS. No VHDL. No mixed sim.
- Dan Steinberg of Integrated Device Technology
NC-Verilog and NC-Sim. We support mixed Verilog/VHDL sims because we
receive some IP from our vendors in VHDL. We code all our stuff
in Verilog.
- Tomoo Taguchi of Hewlett-Packard
NC-Verilog. No mixed Verilog/VHDL
- Javier Jimenez of DS2 Spain
NC-Verilog and VCS
- Ajit Madhekar of ControlNet India Pvt Ltd.
Synopsys VCS. Dont use mixed simulator.
- Luo Min of Northwestern Polytechnical University, China
We use Modeslim VHDL. We don't use mixed language at this time.
- [ An Anon Engineer ]
We use NC-Verilog, Modelsim, VCS across different sites. We also have
mixed Verilog/VHDL environment because of legacy VHDL code. I want to
speak for NC-Verilog because that's the one we use mostly at this site.
Impressed with performance gains we have been seeing with NC-Verilog.
Negative timing checks has become an issue with smaller geometries and
Mux-D flops. NC-Verilog has done a great job of supporting them without
performance decrease from versions 4.1 and later.
Coming back to the question of age-old golden simulator Verilog-XL, we
almost moved away from Verilog-XL. One complaint from me is that
NC-Verilog error reporting mechanism should improve. Lots of our
engineers use Verilog-XL when NC errors out.
- [ An Anon Engineer ]
Using Cadence NC-Verilog and Modelsim simulator. Our project does not
use mixed simulations
- S.K. Rajadurai of Lattice Semiconductor
1) Aldec 6.2 running under Windows XP on a 2.4 GHz dual-Xeon Dell
workstation
2) Modelsim 5.7g running under Windows XP on a 2.4 GHz dual-Xeon
Dell workstation
3) Cadence NC-Sim running on an HP server
All are mixed licenses and the project requires mixed.
Almost all of the RTL designers write in VHDL whereas most behavioral
models and all gate level netlists are in Verilog.
Aldec is by far the best user interface. It is easy to set up a project,
include libraries, assign the top of a hierarcy at any point in the
chain, restart simulations, trace dataflow, and debug. No scripting is
required at all -- the tool hides all of this from the user. I literally
cringe when I'm forced to use other environments and in fact still use
Aldec for the capture part when I'm simulating in Modelsim. My flow is
to initially use Aldec for RTL mixed simulations to debug the RTL and the
testbench. Previous versions of Aldec would sometimes crash on a Verilog
gate-level design so in those cases Modelsim is used. But the problem
with both Aldec and Modelsim for gate-level is that they are too slow, in
which case we use NC-Sim for final gate-level simulation with a debugged
testbench. NC-Sim runs 20-30 times faster since it is machine compiled.
- John Dean of Philips Research USA
We use the Aldec dual language simulator. The reason is that we design
in VHDL and the netlists we get back from the design house we work with
are Verilog.
- Willem Sloof of Philips Microdisplay Systems
We are currently using Aldec's Active-HDL. We only use the Verilog
simulator because we use Verilog for our whole design.
- Peter Tan of Transcore
Aldec AHDL EE, and Modelsim PE. Aldec is the one I use most, as it is
easier to use, has better integrated features, and as a design entry
tool is light years ahead of the quaint editor in Modelsim.
Occasionally, I do mixed simulation because of customer requirements
or IP, but most of the time I stick to VHDL. My work is pretty much
VHDL unless the customer insists on Verilog and is willing to
pay extra for it.
- Ray Andraka of Andraka Consulting
We use Aldec Active-HDL Pro. We don't do mixed HDL simulation.
Everything we have is in VHDL.
- Michael Condon of the Naval Research Lab
Aldec Active HDL. We use VHDL only simulations.
- Mike Murphy of Syracuse Research Corp.
Aldec VHDL Simulator. No mix simulation.
- Reza Shirali of Orbital Sciences Corp.
NC-Verilog and NC-Sim from Cadence. We used to use VCS in the past,
but after we saw a major bug in VCS several years ago we changed to
Cadence and never used VCS again.
- Yuval Itkin of Metalink Broadband, Ltd.
We use MTI and NC-Verilog. We do use little bit of mixed Verilog/VHDL
simulations because of having some legacy designs in VHDL which we plan
to convert to Verilog in future.
- Mohammed Zaman of Analog Devices, Inc.
NC-Verilog. No mixed sim.
- Sachin Mohan of Cypress Semiconductor
We use mixed languages for board-level verification. FPGAs are designed
in Verilog but our off-the-shelf components are modeled in VHDL. Verilog
works fine for synthesis but VHDL seems to work better for behavioral
code and for SDF backannotation.
- Rick Munden of Siemens Ultrasound
We use Cadence NC-Sim 5.1-s6 mainly as a VHDL simulator. Sometimes we
use mixed Verilog/VHDL simulations because some IPs are in Verilog.
- [ An Anon Engineer ]
NC-Verilog: Solid tool. I would like to see better integration with
whatever TestBuilder evolves into. And, I would like a better way or
more refined way of managing transactions. Very manual, very clunky
at this point. Perhaps look at integrating with assertions? I think
this is an issue for all simulators that support the concept of
transactions. The only issue we ran into on our design was with some
of the behavioral "Smart" models provided by 3rd parties. The Smart
models were not supported on Linux. This kept us from taking advantage
of the Linux performance increases on NC-Verilog.
- Mike Bly of World Wide Packets, Inc.
We currently use NC-Sim. We have mixed language simulations. We are
primarily a Verilog house, but most of our external IP is VHDL. We've
just been able to start using VCS-MX. We think Cadence currently has
the better debugging environment.
- Maynard Hammond of Scientific Atlanta
We use Synopsys VCS. We have a couple Modelsim licenses around when we
need to do some sanity checking, but they are seldom used. We
transitioned from VHDL to Verilog more than 6 years ago, and I haven't
touched VHDL for well over 5 years.
- Jonathan Craft of McData Corp.
We are forced to use NC-Sim for all sims. Yes, we also do mixed sims.
I would prefer to use MTI, hands down. NC-Sim is a cluster-fuck.
- [ An Anon Engineer ]
We use Modelsim, and we do mixed Verilog/VHDL simulations to support
external IP. Our internal IP is VHDL. We like Modelsim's integrated
Tcl support, since we write our testbenches and verification scripts
in Tcl, using Modelsim's WHEN statement to synchronize the scripts
with the hardware. We looked at NC-Sim's Tcl support, it seemed to
be a worthy attempt but not as comprehensive or as easy to use as
what Modelsim has.
- [ An Anon Engineer ]
We are 100% Verilog and use VCS. Our software group uses a simulator
from Carbon Design.
- Nathan Dohm of StarGen, Inc.
Cadence NC-Sim, Verilog-XL and sometimes Mentor Modelsim.
Mixed Verilog & VHDL, due to inherited VHDL RTL IP.
- [ An Anon Engineer ]
Both VCS 7.0 and NC-Verilog 4.1. Simulation speed is roughly equal.
- [ An Anon Engineer ]
We are using Modelsim. Projects are done in VHDL. We need a mixed
VHDL/Verilog simulation to combine test benches written in VHDL with
gate level Verilog got from synthesis tool or for the 3rd party IP
blocks available just in Verilog.
- Premysl Vaclavik of On Demand GmbH
VCS - Verilog only
- [ An Anon Engineer ]
Recently moved from a mix of Cadence NC-Verilog and Synopsys VCS to only
using Synopsys VCS. We don't do mixed language sims anymore as all new
designs are Verilog. We do have a few Mentor licenses but nobody uses
them much unless we need to use it because an end customer is using it.
- Samuel Russell of Ceva, Inc.
Mentor Modelsim although a few of our designs created too large of a
memory footprint for our machines. We then had to switch to VCS to get
the sims to run. We used mixed Verilog and VHDL. Normally we're a VHDL
house but most of the IP we purchase uses Verilog.
- [ An Anon Engineer ]
NC-Sim. Yes, we do use mixed Verilog/VHDL simulations all the time
because our chips integrate IPs from various sources, written in both
languages.
- Frank Ghenassia of STMicroelectronics
Primarily MTI and Synopsys VCS. We do mixed simulations because we have
a mixed bag of IP blocks (legacy blocks that are added to new blocks,
etc.) and some legacy blocks are in VHDL... otherwise we would be
pretty much a Verilog center.
- [ An Anon Engineer ]
60% of the company uses Cadence NC-Verilog & NC-VHDL
40% of the company uses Synopys VCS.
Mostly due to historical reasons - company acquisitions.
We have mixed Verilog/VHDL simulations. One product line has
historically been VHDL. Another product line has historically
been Verilog.
- [ An Anon Engineer ]
Modelsim and NC-Sim. We use mixed Verilog/VHDL because of purchased
VHDL IP and in-house Verilog IP.
- Carl Harvey of Cirrus Logic
We use Modelsim PE and SE. We use mixed Verilog/VHDL for gate level
simulation for increased performance.
- [ An Anon Engineer ]
We are using Modelsim. We use mixed simulations when foundries give us
post-route designs in Verilog and our test benches have already been
developed in VHDL.
- Tim Ma of Mykotronx
We are using NC-Verilog. We don't do any mixed Verilog/VHDL simulation.
- Laurent Claudel of Wavecom
Verilog - Modelsim. Some mix of VHDL due to some cells available from
vendors only in VHDL.
- Boaz Ben-Nun of Starcore DSP
Our current project uses NC-Verilog, and the previous project used
Synopsys VCS. We use Verilog exclusively.
- [ An Anon Engineer ]
1. Modelsim VHDL
2. Aldec Active-HDL (for students - considered most user-friendly)
3. NC-Sim VHDL
We don't do mixed Verilog/VHDL simulations.
- Wim Meeus of Universiteit Gent, Belgium
Cadence Affirma-NC. We do use mixed simulation due to IP developed in
different locations in different languages.
- [ An Anon Engineer ]
My project uses Cadence NC-Verilog and also good ol' Verilog-XL. XL
only because I am too lazy to type 'NC' and also because I get less
log file header to page down through than with NC. We have access to
VCS, but don't use it, because of no need. How many simulators does
one need...?!
- Michiel Vandenbroek of China Core Technology Ltd.
MTI, yes mixed, because we use VHDL and every IP vendor on the planet
uses Verilog.
- [ An Anon Engineer ]
Modelsim and VCS, we just use Verilog
- Gao Peng of Tongji University, China
NC-Verilog from Cadence. When we have to do mixed (because of some
legacy IP in VHDL), we use ModelSim.
- [ An Anon Engineer ]
Synopsys VCS, Verilog only. VHDL is for people with legacy
infrastructure that they can't afford to undo.
- [ An Anon Engineer ]
We use Modelsim and Cadence. We have mixed VHDL/Verilog; mostly due
to legacy code.
- Christine Gerveshi of Agere Systems
No mixed mode, we're strictly Verilog.
- Inder Singh of iVivity, Inc.
Synopsys - VCS. No mixed mode.
- Chandresh Patel of Ciena Corp.
Cadence. We use mixed Verilog/VHDL simulations. IPs in Verilog,
design in VHDL.
- Stone Shi of STmicroelectronics
Verilog ONLY.
- [ An Anon Engineer ]
We are evaluating tools for our next project. I think it will be
VCS or NC-Verilog. Unfortunately the cheaper Modelsim tool is
outperformed pretty badly by the others
- Sandro Pintz of Precision IO, Inc.
Mentor's MTI for VHDL RTL verification. VHDL-testbench/Verilog-netlist
for gate level verification.
- Hsing Hsieh of Hitachi
Synopsys VCS. No mixed mode.
- Mark Andrews of EFI, Inc.
VCS and MTI -- sometimes if we're working with coreware in VHDL we also
ensure that our delivered coreware works with VCS, MTI, and NC. We've
dropped Verilog-XL.
- George Gorman of LSI Logic
VCS and MTI; MTI replacing VCS.
- [ An Anon Engineer ]
Internally we use Verilog, we use VHDL to support FLI useage and a
partner who uses VHDL.
- Bill Dittenhofer of Starkey
We are using VCS and Modelsim. We don't plan to do any Verilog/VHDL
mixed simulation. We bring in the Modelsim because one of our partner
uses Modelsim and we want to make sure that our RTL codes behave the
same in both VCS and Modelsim.
- Edmond Tam of Global Locate, Inc.
We use Cadence NC-Verilog simulator. Verilog only.
- Jithendra Madala of QuickSilver Technology
Synopsys VCS. Verilog only.
- Don Monroe of Enterasys Networks
Cadence simulators. Mixed language yes because of IP carried down from
project to project, but moreso because half the group was originally
VHDL and half was Verilog, and no one will change. :-)
- Jerry Roletter of the Naval Air Warfare Center
Verilog only. VCS.
- [ An Anon Engineer ]
We use Modelsim with VHDL/Verilog. Our designers prefer Verilog, and
VHDL is required to model our analog devices.
- Jim Lear of Legerity
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