( DAC'18 Item 9 ) ------------------------------------------------- [05/17/19]
Subject: Movellus beats out True Circuits PLL/DLL IPs as #9 "Best of 2018"
PLL PAIN SHIFTING: One quiet -- yet painful -- side to modern SoC clocking
schemes is because of all the messy *unrelated* clocks (at different phases
and different frequencies) you're required to use PLLs between these clocks.
And after that, there were only TWO ways to design.
1. Buy 3rd party hard macro PLLs from dedicated 3rd party vendors
like True Circuits, Inc. or Silicon Creations or Analog Bits and
then you mold your chip design around these PLLs.
- OR -
2. Roll your own custom PLL that's tuned to your specific chip;
and hope all the man-hours and schedule delays involved pay off.
(This is, mold your homegrown PLL around your chip design.)
Either way, there's multiphasic multifrequency clock related pain involved
with chip design that you can't avoid -- you only get to choose *where* you
get to feel that unavoidable pain.
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TWEAKABLE PLLs/DLLs: A clever fix to this pain shifting conundrum is to use
a totally new piece of digital IP that mimicks how an analog PLL/DLL works.
It's by a company called Movellus and it's silicon proven PLLs at 6 Ghz in
10nm, and DLLs at 1.3 Ghz at 7nm. "We can go faster and smaller! This is
just what we have now!", claims Mo Faisal, CEO of Movellus. (And Mo is in
good company. Word on the street he got $6 million in Series A funding from
Intel, Stata Ventures, U. Mich., Sandhill Angels, and Candou Ventures. And
this 2nd round was driven by Ray Stata, the Chairman of Analog Devices.)
SMALLER/COOLER: A weird fun fact is since the Movellus PLLs/DLLs are 100%
digital, they don't need the big resistors/capacitors associated with
analog PLLs/DLLs; so they use significantly less power and real estate.
Going against the TCI equivalent, the Movellus PLL at 1 GHz or higher is
4X smaller and 10% to 20% less clock power. But go to 500 Mhz or lower
IoT designs and Mo's PLLs shine at 8X smaller and up to 10X lower power.
On a personal note, Mo was on my DAC'18 Troublemakers Panel last year, too.
Movellus Mo's 6+ GHz 100% tweakable auto-generated PLLs/DLLs/LDOs
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QUESTION ASKED:
Q: "What type of IP (hard/soft/VIP) INTERESTED you at DAC?
For what specific protocals/uPs/memories/standards?
What company made the IP you're interested in?"
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Movellus PLLs & DLLs
My company purchased two 7nm IP from Movellus for our data center chip.
- Phase-locked loop (PLL)
- Delay-locked loop (DLL)
When we were looking, there were no off-the-shelf IP available at 7 nm.
Everything is still in development. So, we faced a classic make vs. buy
decision.
Our fundamental reasons for deciding to go with Movellus were:
- Movellus digital approach lends itself to good PPA
- Their IP wasn't too expensive
- Their delivery schedule was better/faster than TCI
Our frequency specs were:
- PLL: 100 MHz to 4.0 GHz
- DLL: 300 MHz to 1.3 GHz
We've taped out, and both Movellus PLL and DLL met our specs, based on
our simulation results. Plus, their delivery was on time. We do not
yet have silicon, but are expect "good looking" 7 nm silicon soon.
Movellus has an interesting technology and ambitious plans. We hope to
leverage that in the future.
Like most small start-ups, they have great support. They're great guys,
flexible, and it's easy to work with them.
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We had Movellus build a custom clock generation PLL for our IoT product
using their all-digital implementation. It's now in working silicon.
Some details below.
We needed a PLL for our system clock generation block; at our node
and threshold voltage none of the off-the-shelf True Circuits PLL IP
met our requirements -- which included ultra-low power and low
voltage design.
So, our options were:
- Try to build it ourselves.
- Outsource it
We shopped around. The driving reason we picked Movellus was that
they could handle our system requirements, namely the strict power
budget and incorporating our low power design environment.
Our chips operate in near threshold regime. For our clock generation
PLL to be compatible, Movellus had to develop it to be near-threshold.
This is important, as IP vendor/services teams are not always aware
of near-threshold design.
Movellus PLL met our specs:
- Target frequency: 200 KHz to 1 Mhz.
- Power: 700 nw at our fastest frequency (1 MHz)
We were also happy that the PLL they delivered was a small, contained
block (200x200 micron), that was easy to handle -- we could drop it in
our chip and be ready to go.
The smaller IP size is because Movellus' architecture uses a digital
filter, which eliminates the need for the resistance and capacitors
that take up a lot of real estate that traditional PLLs have
(either on- or off-chip)
Our project was early in Movellus history. Since then, Movellus has
refined its automated analog IP generation technology. We haven't yet
experienced their now faster turnaround time, but we understand what a
big advantage that will be.
1. Meeting tapeout. The sooner we get the PLL get it in our
system, the better. You must get power and clocks right or
you are in world of hurt.
2. Exploring different processes. PLLs are particularly dangerous
to port to new processes as the custom circuits must be
recreated.
Movellus support was great. They were ready and waiting to support us
when our first chips with their IP came back and they even came over to
our lab to support our bring up efforts.
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Movellus PLLs & DLLs
Our company builds machine learning SoCs. We are using several low-
power PLLs and DLLs from Movellus in "low node" FinFET. Sorry
we can't be more specific, John.
Movellus PLL
We needed several modifications to the TCI PLLs available off the
shelf. For example, we needed the PLL to have a glitch-free clock
MUX that would support our dynamic voltage & frequency scaling
(DVFS) design, so we could change power modes quickly.
We chose Movellus to build that PLL because:
- They had silicon-proven PLLs at the specific (unnamed)
advanced node we needed.
- The Movellus guys were able to do the modifications we needed,
including a super-fine frequency resolution, with only a
3-month delivery time.
- Movellus' digital implementation was also part of our "agility
calculation". Since we were still refining our clock
architecture at the time, we submitted in our Statement of Work,
we anticipated the possibility of further changes.
Because of their digital implementation, we assumed they could manage
minor modifications during the design process.
We haven't taped out yet, but so far, they have met all our critical
PLL parameters, including agility, and have been easy to work with.
We have meetings with Movellus about every other week to stay in sync.
Movellus has also been willing, even eager to review our clock
architecture and make suggestions.
Movellus' DLL
Our original clock architecture did not include a DLL. Late in the
design we realized that moving an asynchronous boundary could both
improve our performance and eliminate a congestion headache.
The only issue was that to implement DVFS we would have to enable a dead
period while relocking the PLL.
After consulting with the Movellus guys, they surprisingly accommodated
our "dead period" option with the best performance but worst schedule
for them: a DLL paired with a PLL. This allowed us to switch the
frequency instantly while keeping clock edges aligned.
They delivered this customized DLL (at additional cost of course) but
impressively within the same project deadline as the PLL.
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Movellus
Traditionally analog blocks are hard to migrate when you switch
technology nodes. Movellus promises analog blocks/IP designed like
digital with as good performance as traditional analog designs. It's
hard to believe.
When we buy analog IP, we buy silicon proven & tested IP. So, I will
wait for silicon proof and if proven, then Movellus does have compelling
technology.
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Movellus caught our eye on the panel. We're having them come in.
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Adjustable PLLs/DLLs from Movellus
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I knew Mohammad back in college. U. Waterloo. He's Canadian yet
he hates hockey.
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Movellus PLLs
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TRUE CIRCUITS, SILICON CREATIONS, ANALOG BITS
TCI CLN7FF x4096 4 Ghz
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We use a lot of TCI PLLs.
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True Circuits 7nm PLLs should be on that list.
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Our IoT uses TCI CLN28LP
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TCI for PLLs. Synopsys for Designware.
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TCI-TN7FFLVT-DSMPLL
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TCI 7nm DLLs
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Silicon Creations 7nm Fracional-N PLLs
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7nm SC PLLs
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Our PLLs are from Silicon Creations
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SC deskew PLLs for our DDR interface
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Analog Bits Frac-N PLL for TSMC 7FF
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Samsung 14LPP Analog Bits PLL
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Faraday PLLs
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