( DAC'17 Item 10 ) ------------------------------------------------ [06/01/18]
Subject: Cadence Innovus dominates Synopsys ICC/ICC2 is #10 "Best of 2017"
ANIRUDH IS CRUSHING IT IN P&R: Just 6 years ago, after Aart acquired his
bitter PnR archrival Magma for $523 million and Rajeev Madhavan was booted
from EDA, a relatively unknown Magma custom design VP named Anirudh Devgan
joined CDNS as the R&D group leader of STA, extraction, and IR-drop under
Chi Ping. In 18 months, Cadence quietly (and with no announcement) put
Anirudh in as SVP of all of digital implementation -- and the CDNS rivals
laughed at the news (ESNUG 534 #4).
Here's the 2013 P&R world that new SVP of Implimentation Anirudh faced:
Then stuff started happening. Big stuff. By 2014, both the EDA rumor mill
and Wall St was buzzing. In his 3Q14 earnings call, Lip-Bu Tan alluded to
getting a "very big contract" with a "marquee global company" which everyone
quickly figured out was Apple and Wall Street confirmed. (ESNUG 547 #7)
Anirudh's "Project Novus" (ESNUG 541 #5) had beat out Synopsys ICC2 in a
secret internal P&R benchmark at Apple!
And that was it. That was the tipping point. Innovus from 2014 to now
in 2018...
Anirudh quietly tells users of "Project Novus" to nullify ICC II
Engineering comments point to SNPS vs. CDNS PNR shakeout at Apple
User benchmarks new CDNS Innovus vs. SNPS ICC/ICC2 workaround
CDNS bigwig launches Innovus with 44 jabs at ICC/ICC2/PrimeTime
Imec does world's first 5nm tapeout using only Cadence Innovus P&R
Anirudh's 32 jabs at Aart de Geus's ICC/ICC2 on his Pegasus launch
8 engineers give the dirt on the Cadence/Imec first 3nm tape-out
AART'S ICC2 FIASCO: But this wasn't all just Anirudh getting CDNS PnR R&D
on track. Anirudh was also lucky. Yea, Innovus got good PPA, but what gave
Innovus a chance was Aart's ICC2 train wreck. It created an opening.
The first mistake was ICC2 was prematurely announced at SNUG'14:
"SCOOP II: Multiple spies report that on Monday, Aart de Geus is
going to announce "Project Newton" IC Compiler II (ICC II) in
his upcoming keynote at SNUG'14 in Santa Clara.
 
From what I've heard, "Project Newton" was a 5 year undertaking
involving 80 SNPS R&D as a re-engineering of ICC for problems
unique to sub 20 nm P&R -- but it ran into organizational issues
I can't get a good fix on. Rumor was ICC II was to be launched
at DAC'13 in Austin, but it wasn't ready then."
- from http://www.deepchip.com/items/0537-10.html
ESNUG 537 #10 & ESNUG 538 #1 give the Day 1 details of what ICC2 had and
what it lacked (placer not working, no MCMM, old router, old CTS, no unified
database) on its SNUG'14 launch. (As I said, it was premature.)
And from 2014 to now in 2018, IC Compiler II just went downhill from there.
Readers on ICC II, ATOP, CDNS EDI, upcharges, Z-Route, 24 months
User benchmarks new CDNS Innovus vs. SNPS ICC/ICC2 workaround
ICC2 patch rev, Innovus penetration, and the 10nm layout problem
Qualcomm, Nvidia, ST join as Innovus users in 2Q15 earning call
By DAC'16, the ICC2 cracks were showing publicaly:
Cooley: "Jim, is IC Compiler II fixed?"
Hogan: "So what do I think of IC Compiler II?
I think Antun doesn't sleep well."
[Hogan looks
at Anirudh]: "I think he's doing a really great job."
- from DAC'16 Troublemakers Panel in Austin, TX
And 6 months after that in December 2016, Antun Domic, who before had ~3,000
employees reporting to him as the EVP/GM of the Synopsys Design Group was
reorged to be the SNPS CTO with 1 secretary reporting to him. (Wiretap 161201)
And a year later by DAC'17, Aart had completely gutted his ICC2 R&D group.
"And they [Synopsys] had a mishap in the PnR engine exchange.
I don't know what the exact numbers are, but Synopsys laid off
200 people between 55-60 years old. So, they cleaned house of
everybody in the prior generation.
So, how long does it take that new IC Compiler II generation to
get on their feet and start being productive and potentially
challenge Anirudh for the lead?
In my experience, writing a place and route system takes 3 to 4
years. We're not going to know if Synopsys has a good team or
not for 3 or 4 years."
- Jim Hogan of Vista Ventures
DAC'17 Troublemakers Panel in Austin, TX
So here's the 2018 P&R world that Anirudh Devgan, the new President of
Cadence, now faces:
"Cadence has been growing a bit stronger in digital design.
We have been growing faster in verification. Things ebb
and flow and go back and forth."
- Aart de Geus, Synopsys CEO, (11/29/2017 earnings call)
TECHNICAL WARNING: Do NOT count Aart out in this game. All the heavy users
of PnR tools -- like Apple, Qualcomm, Samsung, Intel, LG, Broadcom, TI, ST,
MediaTek, Nvidia, etc. -- will eagerly swap out PnR tools for better PPA.
Right now Innovus is winning. That means Cadence gets the big $$$ for it.
For now. If Anirudh's R&D drops the ball and Aart's new R&D guys write good
code... well, you get it. EDA is a SW race that doesn't end. You never
100% win nor 100% lose. It's all just "who's ahead now?"
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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Cadence Innovus
- Very good runtimes. Around 25% faster than ICC using similar
# of CPUs
- Tends to yield slightly more favorable PPA results compared to
ICC, significantly so out-the-box.
- Best in class placement engine. Less likely to cause high density
hot-spots, particularly around macros or other floorplan
obstructions. Also tend to see less global route congestion
issues.
- Tighter correlation to signoff. Reduction in implementation
runtimes means time associated with signoff closure is ever more
critical. Integrated signoff engines help and really are a must.
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Overall Innovus has been a turnaround for Cadence's digital
implementation compared to a few years ago.
- It's strong for CPU/GPU designs - good PPA, better than SNPS
- Cadence Innovus is doing well at 16nm, 10nm, and 7nm advance nodes
- Excellent for designs with ARM cores.
Innovus seems to be gaining market share -- e.g. is in Apple, QCOM,
BRCM, MediaTek, and HiSilicon.
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We've used Cadence Innovus for place and route for a few years.
We currently use it for high-performance designs, plus for previous
projects focused on area and power. We've done 28nm and 45 nm designs,
plus Cadence supports the double patterning at 16nm -- they've improved
the extractions and taking the fills.
Innovus is much faster than Encounter was, e.g. on a 1 Million instance
block.
Cadence continues to improve it:
- It's strong for CPU/GPU designs - good PPA, better than SNPS Most
of the time I use the multi-threaded options and giga
optimization. We've been getting 30-40% runtime reduction.
Innovus takes the most time during post route optimization. We
use multiple CPUs on the same host.
- It's strong for CPU/GPU designs - good PPA, better than SNPS
Integrating clock tree synthesis was a major upgrade.
- It's strong for CPU/GPU designs - good PPA, better than SNPS Since
the engines are the same between Innovus and Tempus timing sign
off, it gives us much better correlation -- though more tuning is
still needed.
--Innovus Integration with Virtuoso--
We do mix digital design and analog design, and our analog team uses
Virtuoso. So we love the Innovus' integration with Virtuoso -- it is a
main reason we are excited about the update. We've been asking for that
integration for a long time, and there has never been a way to do it
smoothly until now. Both tools access a common database through Open
Access (OA).
We used it successfully for our most recent chip and will continue to do
so moving forward. What we do:
- Implement the design using Innovus
- Save it in the Open Access database
- Our analog team opens the same layout in Virtuoso, adds extra
clock nets, and does the simulation in Virtuoso.
Cadence gets us 80% there with their current integration. What they can
improve to get to 100% is the transformation of the netlist. Right now,
we must do some post-processing to have all the views needed for
Virtuoso. Even so, the data transfer is much easier.
Also on our wish list for the Innovus/Virtuoso integration is library
availability from third parties. We currently must convert the
libraries into OA, which sometimes requires manual intervention.
Getting library providers to create OA versions would be great.
We've noticed that bigger companies use both CDN Innovus and SNPS ICC in
their push for performance and area, but smaller companies with analog
mixed signal designs use the Cadence flow -- it's easier for them.
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We've been using Cadence Innovus since we ran our eval 1-2 years ago.
(We previously used Synopsys ICC and Encounter, then moved to ICC and
Innovus.)
Anirudh has done a great job in making Innovus fully distributed, i.e.
multi-CPU & multi-threading. I haven't needed to use it yet, but he
also did good work in this area in the past Magma in SPICE.
The PPA results are the most important for us, and we get better results
(low power and timing) from Innovus than what we do for ICC.
Our designs use advanced nodes -- in the teens. We use Innovus in corner
cases where we have stringent timing.
Cadence is a different company with Lip-Bu -- and now also Anirudh.
And it's making a difference in the market.
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Innovus
Innovus is strong for deep nm physical implementation. Any
implementation system must get results, but Innovus provides the best
power, performance & area (PPA).
In addition to providing advanced routing, clocking, floor planning,
Innovus' fully distributed system gives much faster turnaround time on
large blocks impossible to do in other systems.
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Cadence Innovus
I talked to Cadence at DAC about Innovus. My impressions:
- Delivers great PPA.
- Seems excellent for adv node designs, CPU, GPU, and SOC with
hierarchical capability, etc...
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We use Innovus on our high-performance designs.
We've seen multiple improvements since last year. Because our last
tapeout was not long ago -- I remember it very clearly, especially
since our design size is about the same.
1. Turnaround time speed up.
Innovus is multi-CPU and multi-threaded, and Cadence improved
a lot of the algorithms for the different engines since last
year.
It now takes us only 4-8 hours to run 2 million instances
through some major optimization steps where previously we did
overnight runs of 12 hours.
This means we can kick it off in the morning and get data back
before the end of day for a potential second submission, which
improves our productivity a lot. Although the actual speed up
isn't a full 2X since last year, even going from a 12-hour run
to even 8 hours means we can now often run it twice in one
day, instead of only once daily.
2. Timing Closure
We used to do a lot of manual tuning with Innovus, and now the
tool handles most of it. For example, our designs used to
also require experience to complete, and these days, less
experience is needed to get it to tapeout quality.
We still do a lot of analysis, but now we spend our time
pushing for additional performance.
3. Integration with Virtuoso for mixed signal
We integrate our digital designs with analog designs done
elsewhere. We used to have to do a lot of translations
between formats.
We can now do the design inside Innovus, then push it to Virtuoso for
checking. Virtuoso shows us errors to correct that we can then fix in
Innovus.
The loop is faster and the process is easier.
Place and Route at a 10 nm process node with FinFETs.
We are doing 10 nm process nodes, and node, and closing timing is more
difficult. With a FinFET process, you have different pattern within
each metal layer.
To keep a high yield, patterns within the same metal layer must be
spaced properly and processed at different times. So they color the
metals -- with finfets, even metal 1 can have 3 different colors so they
don't conflict, i.e. Metal 1 color 1, Metal 1 color 2, Metal 1 color 3.
The tool must handle all this during routing. Innovus can handle this
correctly. That's important -- it would be very expensive to find out
during DRC checking that the coloring is wrong -- we'd have to go back
and start again.
We get more requests for Innovus experience now. (We are a consulting
services company and work with a lot of customers -- they pretty much
use either Synopsys or Cadence for place and route.)
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Cadence Innovus
I've heard Cadence is winning the majority of benchmarks now. Their
relationship with ARM and TSMC seems to be paying off big time in market
traction.
Two critical angles to improved turnaround time: 1) TAT for debug,
floorplanning and constraint iterations, and 2) Final TAT for block
signoff.
Innovus Pros:
Innovus is primarily focusing on improved threadability -- specifically
being able to run parts of flow which were previously discrete steps in
parallel. This is fine for full P&R runs for final block closure/final
dash TAT.
The focus on enabling larger capacity designs in Innovus is in the right
direction. I would say that they have raised the bar in the past year
somewhere between 1.5-2.0x in terms of number of instances for the same
machine footprint.
There is clearly an ability to get good improvement up to 8-12 cores and
continued incremental improvement up to 24 (possibly more).
It is increasingly hard to find missed optimizations in the tool. In
advanced nodes we still see a lot of post-route optimization needed and
ECO cycles. They can do more to improve post-route optimization tricks.
Needs Improvement:
I'd like to see improved debug around constraint and floorplan
refinement, which is where our designers spend most of their time.
Would be great if it could stop mid-flow step if bad
timing/congestion/etc. was present so the designer could debug
immediately instead of waiting for it to compete the full flow.
Tool needs improved "unit-level" testing/quality as we still get dinged
by front-line PD team due to regression escapes.
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Innovus and ICC2.
For the past 2 years Innovus generally gets better PPA for us.
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ICC2 + Innovus
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We're still an ICC house. (28nm)
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IC Compiler 2
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