( DAC'16 Item 10 ) ---------------------------------------------- [06/06/17]
Subject: Cliosoft, Indago, Blue Pearl, Magillem, Runtime, Breker, Frontline
SPRING CLEANING 33: Yup, the new DAC is in 12 days, so what better time to
clear my queue of these 33 different leftover tool user mentions?
I like 33. In college, 33 is the mystery number on the Rolling Rock beer
motto. The 33rd is the highest degree you can get in Freemasonry. The
Saigoku Kannon Buddhist Pilgrimage goes to 33 temples in Japan.
The divine name "Elohim" appears 33 times in the Book of Genesis. In
the first episode of the 2004 remake of Battlestar Galactica, the Cylons
attacked every 33 minutes. And there are 33 deities in the ancient Hindu
Vedic religion of central India...
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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Cliosoft SOS & Visual Diff
One of the tools which we like is the Visual Design Diff tool from
ClioSoft. I am currently using it at my current startup where it has
become a "must have" tool. The benefits outweigh the $$$.
With Visual Design Diff, we quickly identifying changes both on our
Cadence schematics and layouts. It informs designers if objects are
added, deleted or modified. It even tells the designer of any
property/parameter changes and what the new value was set to.
It helps our layout engineers tremendously as they do not have to do
"forensic investigation" to find out how their schematic was modified.
The layout engineers are also able to quickly determine layout changes
without running XOR. Of course, Diff is not a replacement for XOR,
but it helps quickly find what changes were done on an ongoing basis.
I think Visual Diff is one of the best tools of its kind in the market.
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We have been using ClioSoft SOS for the past five years for design data
management at Lattice. Their support team helped us migrate from
our existing solution to SOS.
At Lattice, Clio SOS is deployed across all our design locations in
Shanghai (China), Hyderabad (India), Manila (Philippines) and San Jose
for both analog and digital designs. What we like:
* Tightly integrated with the Cadence Library manager for custom
digital/analog designs
* Handles ADE-XL cell views efficiently
* Links-to-cache helps us with network disk space usage per user
* Remote site caching gives virtually primary site like performance
We also use Cliosoft SOS Web to manage project related documentation
files like docs, pdfs and xls sheets. Our analog design teams
especially like Diff tools to quickly to find incremental changes.
This year we saw SOS7 at DAC and liked its capabilities. We evaled
SOS7 and have started to migrate to SOS7 which provides better
performance. We had some initial setup issues but we have made
quick progress and are deploying it on our projects. Right now it
looks quite promising.
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Excellicon vs. Fishtail
CONMAN! CONMAN! CONMAN!
The best was undoubtedly the ConMan tool from Excellicon. We are a
telecom company thus use many external IP's in our SoC's. Our
problem is always building the top level constraints using information
from the block level IP constraints.
This process is very laborious and takes about 3 to 4 months with many
iterations. Me and my team attended the Socionext and ST presentations
at DAC which talked about constraints promotion using Excellicon ConMan.
All the stuff that the talks mentioned was being done manually by us.
We saw the Excellicon demo and were impressed.
We also visited Fishtail and Ausdia. Their demo of constraints
promotion & demotion seemed more like simple hierarchy manipulation
with no intelligence built-in. Neither impressed us.
After DAC we evaluated Excellicon ConMan and ConCert and ended up
purchasing both. Our constraints development schedule is now reduced
from 4 months down to a few days.
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Fishtail Confirm & Refocus
We had drama due to missing constraints and multicycle exceptions that
ended up causing silicon issues. Fishtail was the best tool to close
those disconnects in our flow. Worked very well with multicycle
exceptions checking and found one that the designer kept arguing was
okay but finally realized it was not. Kudos to the Fishtail tool for
finding this bug before we taped out.
Their Refocus tool is also very useful. We also found the verification
assertions generated by Refocus well thought through and saved designers
time in reviewing violations till verification shows a clear issue.
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Questa RDC, Cadence Indago, Verifyter Pindown
The other new tool capabilities that interested me was Questa RDC.
I described our reset domain crossing issues to Mentor and Atrenta
and then Mentor came up with a decent solution for the not very
well understood reset domain crossing issues that lurk in asynch
reset chips.
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Indago from Cadence. We're working in a top level testbench which
is complicated and reruns take a lot of time. We're hoping that
Indago can help with better tracing, debug and we can take
advantage of the virtual reruns to improve turn around time.
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Pindown from Verifyter. We saw marketing information a year ago.
At the time we were working in a block level verification environment.
There was a top level environment but it was limited and focused on
interconnect testing. In our block level environment there were
10 people but everyone was very familiar with what was being checked
in and how it impacted others.
We've transitioned (long story) into a single top level UVM environment
where there are 30+ people checking in code. Trunk stability is a
big problem since it's hard for everyone to run enough seeds before
checkin. We have home grown trunk health monitoring, but that doesn't
help is track down the issue.
We're hoping Pindown might be able to help.
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Methodics vs. IC Manage
Methodics WarpStor - Content-aware NAS. It dramatically reduces user
workspace storage requirements and creation time through the use of
"masters" and "clones"
- Create 100+ GB workspaces in seconds
- Save over 90% disk space for design workspaces
- Works seamlessly with NFS and eliminates bottlenecks
- User mounts workspace rather than copying it
- On the fly diff management as opposed to NetApps nightly diff
management or 20-30% overhead on the fly diff management
- Workspace creation in seconds
IC Manage PeerCache - Software solution to caching SVN workareas.
Uses our own hardware.
- Uses disk as cache on the client machine.
- Only loads metadata. As users read data, it downloads
to the client, then all clients on that host have
instant cache access to that data. The cache then
maintains the differences between the data. So only
take the populate time hit once, and only for the files
needed, then only local disk access delay.
- Costs ~$1000 per host computer.
- It is a bring your own hardware software solution that
accelerates NetApp. It speeds up all your project data,
both managed and generated files, and speeds up all DM
systems.
- NAS Filer Storage savings
- Speed improvement
- Massively parallel Workflows
- With parallel workflows, engineers no longer have to wait
for someone else to finish with their physical copy.
With PeerCache any user can now clone any authorized workspace at any
moment in time -- even a terabyte-sized full chip workspace. The
clones occur in near-zero time, and include both managed and generated
data. No additional storage is consumed until changes are made.
But since IC Manage decided not to support SVN, this no longer is a
viable solution for us.
[ Editor's Note: Shiv just texted: "We're supporting our existing
Perforce customers first, but will support SVN, too." - John ]
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Cadence RocketSim ("Xcelium")
RocketSim is 6x to 20 faster mulitcore RTL & gate-level simulation
- RocketSim offloads most time-consuming calculations to an ultra-fast
multithreaded engine. Unlike hardware based accelerators, RocketSim
works from within the familiar simulator environment and runs
alongside your existing test bench -- eliminating ramp-up time while
providing 4-state bit-precise results.
- Currently, Rocket sim does not accelerate testbench primitives
- It splits Verilog simulation into multi-threads on 100's of regular
multicore Intel x86 XEON servers. What they got benchmarked 23X
faster vs. Incisive. Does gate and RTL sims. Compiles 1 billion
gates in 2 hours. 4-state-logic for X. Full System Verilog and
accelerates SVAs.
CDNS renamed it to "Xcelium". It runs on 8 core Linux box ran 4X faster
than Incisive on a single core Linux machine. For a 400 million gate
design (Fat Man), Xcelium on 6 cores ran 9.3X faster. That is, the
larger the design with the most activity the testbench stimulus, the
better speed-up Xcelium got! When 400 M gate Fat Man was doing high
activity DFT gate-level simmed 30X faster.
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And a bunch of other random other tool mentions...
Pulsic Animate:
- Uses primitive P-cells.
- Highly constrainable
- More of a routing aid then an auto router
- Can work sort of like your standard graphics editor
- Reads and writes OA databases
- Very fast to get to a simulatable netlist with all parasitics
- Multicore
- $50K seat
It is very visual, Pulsic Animate visually shows many layout options
all at once that user can pick from.
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Blue Pearl for FPGA CDC:
Very intuitive
- Checks clock crossings
- Looks very powerful
- Looks for common synchronization errors
- Very graphical. Show all your issues in a schematic
- Checks state machines and state space
Primary theme was ease-of-use and because CDC FPGA customers have
complained that other tools are hard to use. Their CDC tool is
purely static and it examines RTL code. The tool is marketed as
a good FPGA static linting & debug tool. Their CDC view is shows
clocks, domains with number of synchronized and number of
unsynchronized signals entering each domain. The BP CDC tool also
generates SDC for clock domains.
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a) Magillem. This may be the only one tool to connect IP-XACT.
b) Synopsys Custom Compiler. Might help our automotive designs a lot.
c) Zuken CR-8000. It's 3D GUI is amazing
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Agnisys register management tool. Very powerful and hungry.
Vtool graphical UVM development/debug environment
Verific: a library of language parsers (VHDL, Verilog, System Verilog,
UPF) for Perl, Python and C++
Cadence Stratus SystemC synthesis is slowly gaining popularity
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Cadence Jasper ABVIP
I started to play with Jasper this year, especially the protocol
checking ABVIP. It really helped us, especially gaining a lot in
productivity as we were able to find a lot of bugs very fast after
the 1st RTL delivery (no need to build a complex testbench).
Then, I also used the Jasper-CSR app, which is a real bug hunter
for register verification. As long as you have the IP-XACT view
of your design, you're be able to setup the tool very fast, and
to find bugs. As an example, I was able to find 2 RTL issues in
a few days on a mature IP, already used in many SoCs.
The reason why I jumped into the Jasper-CSR world is that each
time it is newly used in my company it leads to find new bugs...
We get our AHB5 VIP from Cadence & Synopsys. No real feedback
on them for now.
For biggest lie I say Synopsys claiming they have a wonderful
toolsuite for functional verification (simulation & formal) but
when it comes to the real world... it is not so wonderful and
lacks support for VHDL constructs especially when you mix them
with other languages (System Verilog).
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MunEDA WiCkeD - Use with Eldo for high sigma on automotive chips.
IC Manage - PeerCache
Runtime - Workflow Xelerator
ICScape - Skipper & TimingExplorer
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a. SkillCAD still has lots of nice tools for ad-on to Cadence.
b. PulseIC Animate looks like it can generate good 1st pass
precision analog layout (multiple variations) for extraction
to check relative LDE/WPE.
c. Frontline tools for very quick/useful checks of IR and ESD.
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Mentor Tessent SiliconInsight for your PC, old tool, but never knew
such a thing existed. Generate and execute ATPG vectors from a PC
through an adapter -- i.e. no clunky ATE located in a different time
zone.
Does a max 64 test in/outs. It's possible to on-the-fly generate
vectors with certain toggle activity, test if the vectors fail, and
if not repeat with higher activity.
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CDNS Perspec / MENT Infact vs. Breker
Cadence Perspec and Mentor Infact are very interesting. The
Portable Stimulus Work Group finally release the first draft of the
syntax. It turns out it's not the same old useless graph that other
has been talking for a few years. It is more like a resource based
constraint resolver. Cadence and Mentor's approach is pretty similar,
just some minor syntax difference that will be ironed out when the
PSWG approve the standard.
I dislike Breker. Their approach to PSWG is awkward, very tedious
and not user friendly at all. I rather write my own C++ code
with Boost Graph library than using the Breker tool. They add
another layer to my code with no added value.
I hope PSWG committee won't pick the standard in Breker's favor.
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And the "Biggest Lie" call outs...
Biggest lie? Atrenta Spyglass Contraints
The efficacy of the Atrenta (now Synopsys) constraints checking tool.
It was very poor at handling multicycle exceptions if it was more
than 2 cycles and the Spyglass AEs kept trying to sell us that it
works well.
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Biggest lie?
Synopsys Formality-Ultra. It's still behind Cadence Conformal.
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