( DAC'16 Item 6 ) ----------------------------------------------- [05/05/17]
Subject: Palladium vs. Veloce -- but no Zebu, no HAPS, and no Protium!
NO ZEBU, NO HAPS, NO PROTIUM: Yes, so Anirudh is drawing aces in his poker
game against Aart in the digital PnR market, but both Anirudh and Aart are
washing out in the war for user mindshare in the FPGA ASIC protyping market.
It's no surprise for HAPS, because other than some incremental capacity
improvements that stem from Xilinx FPGAs getting bigger, HAPS has had no
real "big" news nor breakthroughs in years.
And, for Aart's Xilinx-based Zebu? Well the gossip has been:
"Well, it appears that Aart didn't launch his new 9 billion gate
Zebu Server 4 box at DVcon'17 after all. It's too embarassing now
that Veloce Strato claims 15 billion. (Oops.)"
- ESNUG email blast 03/01/2017
But Anirudh is equally embarrassed here, too, because nobody stood up for
Protium, his 2 year old FPGA-based ASIC prototyper, in this "best of"
survey either. Oops!
But to be totally fair to Anirudh, he didn't get SVP ownership of the
digital verification side of Cadence until Feb 2016 -- just 4 months
before that DAC -- so he can't be embarrassed too much for this one.
Anyway, long story short: none of the FPGA-based HW simulators got any
user mindshare at DAC'16. FPGA was lose-lose for Aart and Anirudh.
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RED STATE VS. BLUE STATE: while Zebu wasn't being noticed by the users,
the good olde Palladium vs. Veloce war are still going quite strong -- with
Palladium Z1 definitely winning the battle in 2016.
After announcing Qualcomm was a big ass Palladium customer, Lip-bu said:
"Total hardware revenue surged to a record high. We gained 29 new
Palladium Z1 logos in 2016, 11 of which were system companies, and
this is the fastest adoption of a new emulation system in Cadence
history. In Q4, several leading semiconductor companies adopted
Palladium Z1, including Cavium and Innovium. ... We expect
another strong year in 2017."
- Lip-bu Tan, Cadence CEO, 16Q4 earnings call (02/02/17)
And the Palladium user comments from DAC here confirm Lip-bu's story.
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In contrast, Wally's Veloce was in defensive mode for most of 2016 with
unconfirmed Wall St. rumors that Intel was getting rid of its Veloce boxes.
But all that bad news may reverse itself with the Feb 2017 launch of the
new Crystal3 uP chip to replace the old Crystal2 chip inside their new
Veloce Strato boxes.
"... in a seesaw business where historically the emulator with
newest uP chip wins this new Strato is a direct in-your-face
threat to Lip-bu Tan's Palladium empire."
- from http://www.deepchip.com/items/0567-01.html
Which will all clearly play out one way or another at DAC'17 next month.
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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CADENCE PALLADIUM
So far none of our firmware guys are bitching about Palladium, so that
must mean it's a top tool for us this year.
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We looked at Palladium Z1 and liked what we saw. For us, Emulation is
the best method to quickly find the system-level critical bugs. The
fast bring-up with the box works well. It lets us stress our DUT in a
realistic environment and useful when debugging design issues.
Palladium Z1 has a smaller footprint compared to their XP2. It has
dynamic relocation with its TPods and gave us 5x faster wave uploads.
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Palldium works for us.
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We're a Cadence house. Palladium, Incisive, Conformal, Jasper
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I guess we must say Palladium to this question because we're one
of Frank's reference customers for it. :)
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My company is running 100's of jobs every day through Palladium.
It's faster compile time is what counts for us.
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New Palladium Z1 customers here.
So far it works as advertised. Fast. Good utilization.
Let's see what happens once the crackerjack CDNS pre-Sales team
finally leaves, though.
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Palladium is hot this year.
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Our OS guys love our Palladiums.
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Palladium Z1 ranks up there. Maybe not #1, but in the top 3.
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We eat, sleep, breathe Palladium here.
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I could heat my cabin for an entire winter in Tahoe with the
heat one Palladium throws off.
We still like it, though.
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Our DAC shopping list:
- Palladium vs. Veloce -- best cost of ownership/best TAT
- Real Intent vs. Atrenta -- best pricing
- VCS/Questa/Incisive -- best pricing
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Indago from Cadence. We're working in a top level testbench which
is complicated and reruns take a lot of time. We're hoping that
Indago can help with better tracing, debug and we can take advantage
of the virtual reruns to improve turn around time.
We're looking at using Indago inside of Palladium.
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MENTOR VELOCE
We design Wi-Fi chipsets. Our existing VCS simulation is too slow
to complete verification on time, and HAPS FPGA prototyping poses
debug and capacity problem.
Late last year, we evaluated the Veloce emulation. Their technical
team was able to bring up our design in 3 weeks, booting OS and
running network traffic.
We use virtual UART and virtual EPGM (Ethernet Packet Generator and
Monitor) to verify our chip's functionality. We use Veloce to verify
data-paths using EPGM and we also currently plan to deploy Veloce for
gate-level (netlist) verification.
With its interchangeable setup to our ICE, we reuse our post-silicon
scripts for testing.
Visualizer gives us a seamless debug environment across VCS simulation
and Veloce emulation.
We also use Veloce for pre-silicon SW validation because of its full
debug visibility -- something we were unable to do earlier with VCS
simulation and HAPS FPGA prototyping.
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I lead the emulation team at my company.
Veloce has proven to be invaluable for debugging some post-silicon
issues which are extremely hard to debug in silicon. That's been its
draw for us.
We also use Veloce for pre-silicon verification, performance testing
and firmware and driver development. We boot Linux OS for our SoC and
do virtualization before tapeout. Veloce has become part of our
tapeout signoff requirement for the server chips we design.
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We use Veloce for our deep debug; trying to find elusive bugs that are
thousand's of cycles into the chip. Jasper and One Spin try to do this,
but nothing beats HW emulation as far as our mgmt is concerned.
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Veloce has amazing throughput. It's compile process sux.
Overall good.
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Jean-Marie says we're supposed to answer "Veloce" to this question.
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We like the Veloce roadmap.
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SYNOPSYS HAPS & EVE ZEBU -- oops! got no user comments!
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CADENCE PROTIUM -- oops! got no user comments!
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