( DAC'16 Item 4 ) ----------------------------------------------- [12/16/16]
Subject: MENT Calypto Catapult single handedly gets #4 for Best of 2016
BADRU, MAN WITH A VISION: First off, going into DAC in Austin was a bit
of a surprise, because about a month before the conference, I had received
a rather angry letter for something I had written back in October 2015
about the Calypto-Mentor reabsorption.
That letter was from Badru Agarwala, the new head of Mentor Calypto and he
was quite angry with me:
"Dear Mr. Cooley,
I've seen you write 3 different references to the Calypto-MENT
transition on DeepChip and you simply will not let it go. Enough
is enough.
Yes, I was the CEO at Axiom. That much is true.
The reason why Sanjiv Kaul left when Mentor acquired Calyto was
not due to any of your crazy conspiracy theories, John. ..."
- Badru Agarwala, Mentor Calypto (ESNUG 560 #5)
But was was interesting about this letter wasn't Badru's rage (I get that
a LOT with some people in my life, just ask my girlfriend) but how he also
then detailed his vision on how he was going to modernize HLS design to be
more like the RTL design flow that chip design veterans know & understand.
Wow! Now that's something worth publishing to 45,000 DeepChip readers!
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AND THEN THERE WAS ONE: A few of years ago Synopsys dropped out of the HLS
game to "pursue other interests". Four went to three. Then Cadence bought
out Forte. Three went to two. Now, this year for the first year ever, not
one survey respondant picked Cadence C-to-Silicon nor Stratus HLS as one of
their "3 or 4 best tools of 2016". Last year 6 users spoke up for Cadence
Stratus HLS. This year, nobody. Not one.
You know what they say, Brett Cline... If the SystemC chicken suit fits you,
perhaps you should wear it. (See ESNUG 537 #3 if you're confused.)
"... the direction Calypto should take now that both Cadence and
Synopsys are both so weak in the High Level Synthesis space."
- Badru Agarwala, Mentor Calypto (ESNUG 560 #5)
"Eighty percent of success is showing up."
- Woody Allen, American actor (1935 - present)
QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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MENTOR CALYPTO CATAPULT
Calypto
We wanted to see how real this vision is that vision guy has.
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Badru. For putting you down a notch.
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Went to check out the new HLS vision by that guy angry at you.
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If Calypto brings SysC into RTL tools, SysC might be worth trying.
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Mentor SystemC -
Wanted to see how real the Badru vision is.
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We want to see how Badru's vision connects to the downstream Synopsys
and Cadence RTL synthesis tools.
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Badru is actually a pleasant man in person. What he said about the
need to modernize HLS to be like RTL design makes sense.
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My VP is skeptical about C-based chip design. If anything will change
his mind, it'll be this Indian guy's vision.
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Badru's vision is a much needed injection of fresh ideas into C.
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Catapult HLS 10.0
We liked the roadmap that the Badru person was visioning about.
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Mentor Catapult HLS 10.0 -- new features & vision
1) Catapult HLS 10 supports a subset of C++ constructs and tighter
mixing of C++ & SystemC. I am particularly interested in SysC
interfaces around C++ blocks with possibility of using SV-like
concurrent assertions in SysC that can be formally proven in
C land but also synthesized in Verilog RTL. This is to play a
big role for us in integration testing; particularly with hand-
written or third party RTL (IP) we see.
2) C linting in Catapult. It's geared for HLS suitability. This
could help since only a subset of C/C++/SysC is synthesizable
in Catapult and there are more optimal ways to write HLS C.
3) They claimed they will integrate C Code and functional coverage
within Catapult (likely an unified coverage database with RTL).
4) Claims improved debug and design visualization, especially on
designs that cannot be scheduled.
5) C/C++ immediate property checking (with CPC).
6) InFact integration with Catapult (to use instead of CRAVE
Accellera SystemC SV-like randomization.)
7) Formal RTL Code/Functional coverage integration with Catapult.
Any dead code or unreachable functional coverage will be back
annotated to C and a counter-example generated.
8) Catapult will support designs with multiple clock domains.
This all finally starts to sound like a long overdue RTL rigor at
C/C++/SystemC level.
It seems that MENT Calypto is building towards an HLS tool ecosystem
to improve front-end C design. It starts to look like RTL is becoming
a back-end, at least that is the vision as I understand it.
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We implemented a custom accelerator for mobile computer vision chips
using Mentor Catapult HLS.
Catapult HLS automatically generated our Verilog RTL from our SystemC
and C++ behavioral source code. We used it as part of our algorithm
and architecture co-design & design space exploration.
Catapult helped us do faster prototyping by:
- Handling the pipelining, resource allocation/sharing
- Having compiler flags & directives to help with our
design space exploration
- Lets us reuse our SystemC/C++ testbench to verify its
generated RTL
- Generating switching activity for downstream Verilog RTL
power analysis with SystemC/C++ testbench
Using SystemC/C++ as our core design language improved our design
productivity over RTL:
- C++ language made both the design and verification processes
easier
- SystemC enabled us to implement complex control modules as
loosely-timed code
- The fewer number of lines of SystemC code reduced our bugs
and shortened our design cycles
- The C++ object-oriented programming capability enabled code
sharing and efficient reuse
We also met our design QoR goals for performance and low energy.
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Mentor Catapult HLS
I saw NVidia's presentation on Mentor Catapult HLS at DAC.
I liked Catapult's power optimization to make smart power decisions,
and its ECO support seems unique.
I was impressed that in only 4 weeks, the NVidia engineer:
- Implemented a few different design variations proposed for
a research paper
- Optimized different parameters in those designs
- Created and tested 24 different architectures, to find
the best one.
The time savings for simulating at the C level vs RTL would be a big
reason for us to switch. So would Catapult's power optimization at
the micro-architectural level. We'll investigate more, I'm sure.
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Mentor Catapult high level synthesis -- based on what Mentor
discussed at DAC. (I haven't used the tool)
- Catapult does HLS power reduction. Nice to do this early
in the design.
- Automating the coverage closure with Questa Covercheck vs.
doing it manually is a positive.
- Faster simulation at C level vs. RTL is an advantage.
It supports both SystemC and C++. We currently don't use either
one, but we've looked at SystemC for TLM.
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Mentor Catapult HLS -- liked their testbench for testing transactions
and TLM.
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Mentor Catapult HLS. It supports both C++ and SystemC, and that is
definitely something we are looking at.
- At a high level, they are the only HLS tool that supports both
languages.
- Catapult is not yet not fully compliant with the SystemC
Synthesizable Subset, though Mentor says they are actively
working on it.
Simulating at the C level gives us a 2-to-3 order magnitude speed-up
over RTL simulation. The results vary by design, but this is typical.
We use Catapult as standalone tool to generate Verilog RTL, so although
Mentor has been integrating it with downstream tools such as Questa
and Cadence verification, that is not necessary for us.
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Mentor Catapult HLS. C simulation performance is much faster than
compiled Verilog RTL simulation.
This allows me to perform a full design space exploration of my
initial design.
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I used DAC to find out more about Mentor Catapult HLS.
It potentially has value, though I have not used it to confirm this.
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I can tell you about Catapult HLS, but my experience generalizes fairly
well to the Cadence Stratus HLS and NEC CyberWorkBench as well (with
some subtle differences).
My starting point is that I'm using Vivado HLS and would like to know
how other tools compare. The strangest thing about my survey of HLS
technologies at DAC is that when I mentioned my use of Vivado HLS to
these vendors and also to users of these tools, everyone dismissed
Vivado HLS as a "free tool". I found this particularly bizarre because:
1) You do have to pay Xilinx for a full version of Vivado
2) AutoESL was an actual company with paid employees (presumably
converting the dollars they were being paid into a quality tool?)
3) It would seem to suggest that an EDA tool's quality is proportional
to what you pay for it. This seems like it would extend to
dismissing all open source EDA (which I have a particular problem
with).
In terms of capabilities, Catapult is a non-starter for me due to the
lack of Altera/Xilinx floating point support. As I understand it,
Catapult requires you to use their own floating point library (for
arbitrary precision, I believe). However, this makes porting existing
code painful and precludes running the source as both x86 and RTL since
I certainly don't want to run Mentor code on an Intel server if I really
care about performance. But this all really breaks down because
Catapult implements the floating point logic in RTL (and doesn't use DSP
or hardened floating point resources). Vivado HLS can make DSPs, so it
looks like I'll be using the "free tool" for the time being.
I didn't dig much further than this, but for completeness, I did
describe some concurrency issues we're fighting in co-sim.
Catapult claims to have ways to deal with what we're seeing. But the
issues are complex, so I'd really need to be hands-on to confirm.
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Catapult HLS (with PowerPro & SLEC)
Mentor integrated its power reduction tool with Catapult HLS.
Combining the Catapult C flow with the PowerPro RTL flows with
their SLEC deep sequential analysis and equivalence checking,
lets them go a step further. The ability to seamlessly generate
from our C++ models into power-optimized RTL is interesting.
If we tried this with Cadence Stratus, you have to combine
different, 3rd-party tools: HLS, power reduction, and equivalency
checking.
Our only major concern is all Power optimization tools can give
suggestions. It is very difficult to manually open HLS-generated
Verilog RTL to insert power-corrected code.
They combine Mentor Catapult and PowerPro and built-in equivalency
checking so you don't need to do checking manually. With the built-in
EC, you can both confirm and trust that the RTL changes made to reduce
power do not break your functionality.
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Related Articles
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MENT Calypto Catapult single handedly gets #4 Best EDA of 2016
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