( DAC'16 Item 2 ) ----------------------------------------------- [12/16/16]
Subject: Real Intent and Blue Pearl get #2 overall for Best EDA of 2016
LOOKING FOR CHEAPER OPTIONS: Roughly 18 months ago, Aart acquired Atrenta
for $100 to $150 million which is 2X to 3X ATRN revenue. His announcing
the deal was the biggest news at the 2015 DAC (which I scooped on 05/05/15,
a full 35 days before it happened in ESNUG 550 #8 -- but I digress...).
Reactions to this SNPS-buys-ATRN news at the time were split. In DAC'15 #8,
a typical naively optimistic and younger engineer said:
"Upside: We will now get SpyGlass and BugScope almost free
as part of our package license buy from Synopsys."
while a typical cynical pessimistic and older engineer said:
"If Atrenta prices go down (which we seriously doubt), we
buy more SpyGlass.
If Atrenta prices go up (which we expect), we're looking
at Real Intent."
And since chip design is by its very nature a cynical pessimistic process
where if it can go wrong, it will go wrong, guess which engineer was right?
No one enjoys being fleeced.
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Hint: this year's #2 Best EDA Tools of 2016 is the Spyglass-alternatives
category. And it's all about pricing. That is, Aart bought Spyglass and
then Aart raised prices 2X to 3X -- which has sent the users shopping!
"Expensive clothes are a waste of money."
- Meryl Streep, American actress (1949 - present)
"If saving money is wrong, I don't want to be right."
- William Shatner, American actor (1931 - present)
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THAT WHICH DOES NOT KILL US: The side effects of a big aquisition like when
Synopsys bought Atrenta are massive in its niche.
- 6 months before Atrenta gets bought, the ATRN sales guys go nuts
trying to sell as much Spyglass as they can. They sign multi-year
deals, etc. -- because this is the end and once ATRN is sold,
they're all going to be laid off anyway. Atrenta management
encourages this sales boost too cause it ups the value of Atrenta
stock; which means a higher ATRN acquisition selling price.
May 2015 to Jan 2016 -- 9 months of a very depressed linter/CDC/X tool market
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- This sudden glut of sales depressed the linter/CDC/X checker market
in two ways:
- "Hey, we just bought 3 years of Spyglass last week
for a good price. Call on us in 3 years"
- "We can't commit on lint/CDC/X tools until we see
how Spyglass skakes out. Call in 6 to 9 months."
Although I don't know if this is *exactly* how the Atrenta-SNPS merger went
down, I've seen these things happen enough to know I'm probably close.
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HAPPY REAL INTENT: So 12 months go by and then DAC'16 happens. A quick look
at the Real Intent booth said eveything. It's the same size as prior years.
And the user foot traffic spoke volumes. (I had to schedule a time to talk
with Prakash Narain, CEO of Real Intent, because his booth was so busy.)
And when I finally got to meet with Prakash, he didn't try to bullshit me;
which impressed me even more.
"That time right before, and 6 months after, the Synopsys-Atrenta
acquisition last year was Hell for us. Nobody was buying linter nor
CDC nor X tools during that time. But the timing was OK for us
because I had my guys focus on getting our next generation tools ready.
We entered beta with these newer tools about 3 months before DAC 2016.
That gave our R&D and FAE's plenty of time to qualify them -- which
meant I went into DAC 2016 with a new GUI, 2x more capacity and 2X more
performance for our linter, CDC, Reset Domain Crossing (RDC), and
X-verification tools."
Prakash added: "For new EDA technology tools, we are the only one who has
a working RDC checker. It's called Meridian RDC. I'm very happy with it.
What my customers say when we show it to them is that the SNPS Spyglass RDC
(an option inside Spyglass CDC), and the MENT Questa RDC tools are both
unusable. Real Intent leads here."
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HAPPY BLUE PEARL: Although Blue Pearl was established 12 years ago in 2004,
and it even first showed at DAC in 2005, Blue Pearl was seen as a weird
social reject amoungst its EDA peers during most of those 12 years. Sort
of like that quiet odd loner guy in EDA high school who nobody understood...
... but then 12 months ago Aart seriously raised the prices on Spyglass.
With a viable much cheaper Spyglass-alternative, EDA users along with their
budget conscious CAD departments developed a very sudden new interest in
the Analyze RTL & CDC tools. I phoned Ellis Smith, CEO of Blue Pearl,
earlier this week.
"At DAC we showed 200,000 lines of synthesizable Verilog RTL
source code for an OpenRISC 1200 (OR1200) design that only took
3 seconds to read and load into our enviroment. It impressed
the engineers on the floor.
Yea, I think we were a little misunderstood at first in EDA
because our intial user base was heavily military and aerospace
electronics houses. The mil-areo guys are mostly into FPGAs
because of fast turnaround time, they're low volume chips, and
their designs are secure on an FPGA -- that is, no one in another
country is fabbing them, seeing what's in them.
We branched into SoC/ASIC tools 4 years ago after a big injection
of cash from a Pennsylvania investor.
Our tools do a full Verilog/VHDL/SystemVerilog RTL analysis simular
to Spyglass and Real Intent. Our difference is Blue Pearl has the
fastest find-fix rate in the industry. Our ASIC/FPGA customers
like us because we can go to any level of granularity within our
Visual Verification Environment. Also, they complain that the
signal-to-noise ratio is too low with Spyglass and Real Intent.
With those tools, they don't have a way to evaluate 5,000 error
messages to see where the real issues in their design are. With
our tool they can easily drill down visually. For example they
can ask for "all dangling nets", and our tool will just show it to
them. Spyglass and Real Intent can't quickly filter down like we
do, which is why our find-fix rate crushes them. I'd suspect we're
5x to 10X faster or more than them on our find-fix rate."
(Ellis also chatted up some compilcated reason why his Blue Pearl CDC was
technologically better than either Spyglass CDC or Real Intent CDC, but
I'll be honest and say I didn't quite get what he was saying.)
MOSTY FPGA, AND SOME ASIC: Snooping I got the impression that Blue Pearl
kicks ass in FPGA linting and CDC. They have the Xilinx, Altera, Microsemi
device libraries -- plus the Xilinx UltraFast methodology built in. They
do full CDC, which goes further than the clock interaction report that
Xilinx does. And Altera and Microsemi don't do CDC at all. Overall in
rough numbers Blue Pearl's business is 70% FPGA and 30% ASIC.
Ellis added: "OK, we can't do RTL sign-off like Atrenta does. Our strength
with ASIC users is we're 1/5th to 1/6th the price of one Spyglass license.
We recommend that you buy 1 Spyglass license for final RTL sign-off, and
then buy in bulk our less pricey Blue Pearl tools for everyday use. That
way you get excellent linting and CDC for a far less cost."
"Watch the costs and the profits will take care of themselves."
- Andrew Carnegie, American industrialist (1835 - 1919)
QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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REAL INTENT ASCENT LINT
With the Spyglass price increase, we're looking hard at Ascent Lint
as a cost cutting substitution.
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Real Intent. We're not happy about the Spyglass price bump.
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MGMT likes the Ascent Lint RTL linter. Saves money.
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We're not a big name logo like Apple or Qualcomm, so we're very low
on the Synopsys-Atrenta support queue. In the next year we'll
probably switch over to Real Intent for better treatment.
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We use lots of VCS licenses. Our verification team thinks it's
smarter to use non-Synopsys linters/checkers. Prbly Real Intent.
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Did an eval of the Real Intent Ascent Lint RTL linter.
- Real Intent is low noise, it only sends out errors and warning
that are real. Lint tools in general throw out a lot of
garbage, and it's hard to sort through.
- Also, Ascent Lint doesn't have duplicates, which helps a lot.
Some of the other tools give the same error - with different
names -- double, triple, quadruple, and even 20 times.
The name of their company makes the point -- they try to figure out your
real intent for the design.
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I've used Real Intent Ascent Lint - it checks RTL source code against a
comprehensive design rule deck aimed at identifying potential issues in
design and questionable constructs which may cause issues in simulation
and synthesis later on.
- I liked its runtime performance, which ranged between around
5,000 - 10,000 gates/sec.
- Ascent Lint had minimal report "noise" with very few false
positives.
Ascent Lint's fast runtime and robust rule set made it efficient at
catching issues early on in the design implementation phase. I'd
recommend it.
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I saw Real Intent's Ascent Lint RTL linting tool at DAC.
The GUI and features looked good. I haven't tested these yet, but do
want to look further at it.
1. Real Intent says they have low-noise reporting so you are not
cleaning up false positives. This was a good feature, and looked
unique.
- It takes similar errors or warnings and prioritizes them, so you
can fix them in priority order.
- The tool has the intelligence to display most critical first and
not show the subjugated ones.
2. Another positive is that Real Intent doesn't have duplicate
reporting.
3. Real Intent comments on fast linting speed. Since most of our commit
flows are only 20 minutes, their linting tool was already fast enough
that the Ascent performance improvement is not a factor for us. It
might be for others.
4. DO-254 high-reliability design rule support - Designs that have
safety features could benefit from this; however, it is project
dependent and doesn't impact my group.
5. Real Intent now has a database-driven debug.
- This is good -- it's a great step to store it there and access
through SQL queries.
- Once a tool creates a database I want to be able to use it. We
prepare a number of of audits. So when Real Intent comes up with
issues and put them in DB, I'd like to see a unique ID, to map to
our system, so it's never reused. I think their ID is only
unique for each iteration of the analysis, so I'm not sure how
it would work, as it could be a lot of records from multiple
runs. Maybe they could have a web interface to query a record,
to reference from other tools.
Real Intent does automatic generation of code documentation and
requirements traceability. We code with VHDL 2008, and Real Intent's
linting support for VHDL 2008 isn't quite there.
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We use Ascent Lint RTL linter.
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We saw Real Intent Ascent Lint at DAC, then did an evaluation.
Real Intent's linter looks for questionable constructs in your RTL
code; things that could be problematic or tend to trip people up.
Ascent Lint was able detected design errors that our other linter
(Cadence Hal) did not catch. The errors were also not detected during
our hardware verification cycle.
Real Intent claims it's linter has less noise than other linters.
However, we couldn't verify it either way because of time limitation.
The GUI for Ascent was a good bit slower than Cadence Hal's.
The Ascent Lint reports were well-organized.
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RealIntent Ascent. It works. I have no complaints.
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REAL INTENT MERIDIAN CDC
Real Intent Meridian CDC checks RTL design for clock domain crossing
issues. I found from direct experience with the tool:
- Meridian's analysis is fast, running at ~4,500 gates/second.
- Meridian CDC automatically identifies clocks in the design which
makes environment setup effortless.
- Meridian's report had less noise than the Spyglass - there were
fewer unnecessary structures in the Meridian report file than
the equivalent Spyglass CDC report.
- Real Intent's CDC gives us good visibility -- we can drill down
in the Meridian debug database for detailed analysis at the
path-level.
Overall, I liked the tool's design setup, performance speed and detailed
debug.
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Meridian CDC - we are running the tool in-house on our platform.
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Realintent Meridian CDC. A very good tool for CDC check, good clock
tree view in the GUI.
It used to use Synopsys Verdi as schematic viewer, and now uses the
Concept Engineering web browser plug-in viewer.
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Real Intent Meridian. Our company is interested in this tool and is
evaluating this tool.
Our own rules can be added under NDA.
Hamed Emami, VP of Sales, used to be a Magma guy and we have a good
relationship with him.
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We evaluated the Meridian CDC last year. The Meridian CDC itself seems
to be a good tool, but the functional advantages are not conclusive so
far. In order to switch tools, we must be convinced that without that
tool we cannot release a new chip.
We decided to continue to use Spyglass CDC for the reasons below.
1) GUI is not conclusive. Although the Meridian's GUI is really good,
we usually share one license. Thus, if one engineer uses the GUI,
others would not be able to use that. It is very inconvenient for
us. Moreover, we have already developed a lot of helper scripts for
Spyglass CDC, and each engineer simply calls one batch command to get
enough formatted log files. It is hard to modify these existed
scripts.
2) Performance is almost the same. Memory consumption and execution
time are similar (both have strong and weak points). Additionally,
even though the Meridian CDC can catch setup faults, it sometimes
overlooks other errors. I am afraid that was because our settings
were not optimal for the Meridian CDC during our evaluation.
3) Pricing would not be discounted. Atrenta was acquired by Synopsys,
and because we currently use a lot of Synopsys tools such as VCS,
Formality, ICC and so on, we receive volume discounts from Synopsys.
Since we are not using any other Real Intent tools today, I'm afraid
Meridian CDC would be more expensive.
Real Intent new features, such as its Meridian RDC reset analysis tool,
is very interesting. However, I am afraid that it would not be enough.
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REAL INTENT MERIDIAN RDC
Meridian RDC. Just saw it in the RealIntent booth. We're thinking
about doing an eval on it.
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I like the reset analysis proposition. Meridian RDC.
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Want to compare Meridian RDC to Questa RDC once we tape out.
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REAL INTENT ASCENT XV
Ascent XV -- X-Propagation Debug for RTL and Gate-Level
Real Intent Ascent XV identifies X-optimism problem during the RTL
design phase.
We have Ascent XV in house. The setup was easy since the tool
automatically recognized the clocks.
For us, the runtime was between 1.5 to 3K gates/second. Also, its
output reports did not have much noise.
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We use the RealIntent Ascent-XV tool. They have a really good AE
lady, Lisa Piper, who gives us exceptional support on it. If there's
something to be known about X's mess up verification, Lisa knows it.
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Ascent XV. We like the idea of an outside tool checking VCS.
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BLUE PEARL CDC & ANALYZE RTL
Looking at Blue Pearl to save on our CAD budget next year.
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Blue Pearl CDC/Analyze
I visited Blue Pearl at DAC to get an understanding of what all they
support.
We currently use Spyglass, but due to Atrenta's change of ownership
(i.e. Synopsys), we most likely will not be able to get the same license
at any reasonable cost.
So we are in the market to evaluate alternatives.
CDC analysis is not a very important part of our design cycle because
our designs tend to be small variations of our core design which is well
understood by the design team. So the chances of errors are low but we
still tend to have a tool available as some customers insist on seeing
such an analysis done.
My impression of Blue Pearl from the brief demo was that it might be
sufficient for us. We don't really require capacity or run it too often
in our flow.
As long as we have a decent way of waiving off undesired messages and
assimilating the waivers in subsequent runs we should be ok. And it
felt like they support that with CDC/Analyze.
The biggest criteria for selecting the tool for us would be cost, as
being a small IP company we view the functionality as non-critical.
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BluePearl Analyze RTL -- since our SNPS sales guy went 2.4X our normal
quote on Spyglass, I've been tasked with finding a replacement tool.
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Might do a Blue Pearl eval. They can do FPGA. Can they do SoC?
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We recently did a demo and evaluated Blue Pearl Software RTL Clock
Domain Crossing Analysis. (CDC/Analyze).
CDC/Analyze identifies where you have issues that need to be corrected
when your design data crosses between clock domains. It also identifies
the type of failure, such as missing synchronizers, re-converging nets,
and combinational logic in synchronizers and before synchronizers.
We use Blue Pearl CDC for FPGA design. Blue Pearl claims CDC also works
for ASIC design, and that it supports VHDL, Verilog, SystemVerilog and
mixed languages. What we found useful in our FPGA:
1. Setup
- The automatic clock and reset identification is very useful,
especially when you are analyzing a design you are not familiar
with. This can be time consuming to do manually, especially for
large designs.
- Understands clock generator blocks to propagate clocks; this
saves you from manually search the code to find them
- Blue Pearl's clock interaction diagram is helps you understand
how the clock actually interacts with the other domain,
including the timing relationship.
2. GUI, Batch modes, Reports
- Initially, we like to set up batch mode for initial analysis,
then use the GUI to look at issues it identifies.
- With the GUI, you can do your debug using their cross-probing
and schematic display.
If you click on an error, it can show you what is causing the specific
error in schematic and/or in source code. In the schematic view, you
can see a color-coded view of only the selected path.
- You can also generate reports in text format. You can select
what you want to include. For example, the tool may find issues
that are correct, but after investigation you determine they are
not a concern for your design. You can set to filter/ignore
those issues, to reduce the noise.
3. Clock Synchronization Schemes
Clock Synchronization requires passing data across clock domains while
maintaining the data integrity and consistently.
You can think of it as handing off a box between two moving cars, where
the first car is going 33 mph car and the second car is going 100 mph.
You must have an exact plan at a specific point in time.
Blue Pearl automatically recognizes common synchronization schemes such
as:
- Double register buffering
- (FIFO) register file based synchronization
- Multiplexed control- based synchronization
Additionally, if you've implemented any customized synchronization
schemes, you can let the tool know, and it won't send back a false
positive failure for it.
4. Gray Cells.
CDC lets you put a high level model for your block to provide enough
fidelity to analyze the CDC without knowing the details. We haven't
used this feature yet, but it will definitely make thing easier, as
otherwise, you don't have an analysis of the clocking data going into
the block.
I'd recommend Blue Pearl CDC/Analyze to others. It's a good tool, plus
Blue Pearl supports Windows as well as Linux; the Windows support was a
major differentiating factor for us in picking them.
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Blue Pearl RTL Clock Domain Crossing Analysis.
Blue Pearl's graphics were good -- the tool collected useful information
and the way it presented the parameters/content was useful.
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Blue Pearl CDC/Analyze
- Very intuitive
- Checks clock crossings
- Looks very powerful
- Looks for common synchronization errors
- Very graphical. Show all your issues in a schematic
- Checks state machines and state space
- Primary theme was ease-of-use because CDC customers have
complained that other tools are hard to use.
- Their CDC tool is purely static and it examines RTL code. They
market the tool is as a good static linting & debug tool.
Their CDC view is a domain diagram which shows clocks, domains with
number of synchronized and number of unsynchronized signals entering
each domain. BP CDC also generates SDC for clock domains.
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Blue Pearl was a little behind on the game; the last I looked, the
analysis result is noisy. Need to do detailed evaluation to see the
difference.
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We use Blue Pearl Analyze RTL with their Clock Domain Crossing (CDC)
option.
We currently use them for both ASIC and FPGA designs. Our primary RTL
language is Verilog, along with some SystemVerilog.
We've used Blue Pearl's Analyze RTL as our Verilog lint checker for
8 years now.
- Our engineers run it as they are modifying and creating new
Verilog IP modules.
- We also run it in regular regressions to make sure new code
changes don't cause unexpected lint problems.
- When we prepare our IP to be delivered to our customers, we run
Analyze as a final check on the processed IP modules to make
sure we don't have any lint issue "escapes" at the time of IP
delivery.
Below are some of the features for Analyze RTL with CDC, and our
experience with each:
1. Full TCL parser
Blue Pearl now has a full Tcl parser mode available. We're
investigating leveraging the standard Tcl parsing flow to give us more
flexibility in how we configure Analyze for different projects, rather
than just using our current single, "standard" configuration for all our
projects.
2. Clock Domain Crossing analysis checks
Blue Pearl's CDC checks include missing synchronizers, re-converging
nets, combinational logic in synchronizers, and combinational logic
before synchronizer.
While we use CDC checking in a standard configuration today, we will be
enhancing our flow with Analyze's latest Tcl-based project flow to allow
us to customize for a full range of our IP core configurations. This
allows us to customize the CDC clock and path constraints, as well as
CDC path waivers.
3. CDC debug with cross-probing and schematic display
We have done some CDC debugging and analysis using Blue Pearl's GUI
mode, and found the GUI to be very useful in tracking down CDC issues.
We occasionally use Analyze/CDC in GUI mode when exploring a more
difficult problem. For example, we have also done some limited use of
the GUI mode to review CDC violations in detail.
However, it is not our preferred flow to use the GUI since our IP
doesn't change with respect to clock domains significantly over time.
So once we understand the basic issues using the GUI, we convert our
flow to a complete script-based batch flow, which their Analyze tool
supports well. 99% of our work with Analyze RTL is script-based.
4. CDC/Analyze User Grey Cell (UGC) for IP-based Designs
Since we create all the RTL modules for our IP core designs ourselves,
and there are no third-party IP modules within our cores, this has not
been an important feature for our projects.
There have been some exceptions where we want to analyze top level
integrations containing third-party models. So we have plans to look
into the User Grey Cell flow in the future.
Blue Pearl has done considerable work to add features to enhance their
Analyze RTL lint checks and CDC checks over the 8 years we have been
using their tool, and we continue to see increasing value of their
product over time. Also, they've been very responsive to our support
requests.
We'd definitely recommend Blue Pearl Analyze RTL/CDC to others. We like
the tools' fully functional batch-based flow, and the flexibility of the
Tcl-based project flow to allow for further automation across design
configurations.
And though we rarely use the GUI flow, when we do use it for detailed
debugging of lint and CDC issues, we find its intuitive and helps to
understand design issue's root cause quickly.
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If it saves us some money we might go Blue Pearl CDC & Analyze RTL.
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