( DAC'15 Item 7 ) ----------------------------------------------- [12/18/15]
Subject: Calypto PowerPro, Apache PowerArtist, but no Atrenta SpyGlass Power
VIC KULKARNI'S 2ND CHANCE: If you look below you can see that in the RTL
power optimization category Sanjiv Kaul's Calypto PowerPro had clearly
"won" DAC'15 as far as the users were concerned.
Sanjiv had everything going right. Calypto was growing 12% every year, a
big Broadcom PowerPro deal is just about close (ESNUG 552 #1), his rival
Atrenta SpyGlass Power was in "being acquired" chaos, plus rumor is ARM
is abandoning Ansys PowerArtist to standardize on PowerPro (ESNUG 552 #8).
That is, Calypto was kicking ass -- right until just 3 months after DAC'15,
(09/15/15) where like the Borg consuming a new civilization, MENT management
suddenly decided to absorb Calypto back into Mentor -- plus cut Sanjiv, plus
cut all Calypto sales and marketing, plus cut some other Calypto staff.
Now Calypto is still has 4 to 6 more months to go before it gets out of its
own chaotic "WHAT ARE WE REALLY DOING NOW??!!!" window. While Atrenta
SpyGlass Power still has 2 or 3 months to go in that same chaos window.
Which suddenly now gives Vic Kulkarni, the former CEO of Sequence who now
owns PowerArtist inside Ansys Apache, an unexpected second chance. How so?
Waaaaaaay back in 2012, the big #1 EDA tool drama at the beginning of DAC'12
was the Atrenta vs. Apache vs. Calypto battle in RTL power optimization.
But a quick 3 months after that DAC'12, Apache PowerArtist was weak in the
post-DAC'12 user survey comments:
SpyGlass Power, PowerPro RTL, with some PowerArtist users at DAC'12
http://www.deepchip.com/items/dac12-01.html
And then by DAC'13, PowerPro moved to #1, SpyGlass Power to #2, while ANSS
PowerArtist completely fell off the radar as far as users were concerned:
It was just Calypto PowerPro vs. Atrenta Spyglass Power at DAC'13
http://www.deepchip.com/items/dac13-03.html
And PowerArtist again stayed missing after DAC'14 of last year:
Calypto PowerPro, Atrenta SpyGlass Power, but no Apache PowerArtist
http://www.deepchip.com/items/dac14-09.html
So why is this Vic's 2nd chance? Scan past those Calypto PowerPro user
comments below. You'll now find Apache PowerArtist user comments (which
haven't been seen in 3 years!) -- with Atrenta SpyGlass Power now being
the new RTL power tool being forgotten by the users this year.
Which begs the question: "will Vic take advantage of this unexpected 2nd
chance? Or will he squander it?"
Other tech news from DAC'15 was "Power App" where MENT Veloce teamed up
with Apache PowerArtist to do emulation fast RTL power optimization; and
(SCOOP!) Calypto has a stealth new tool called "PowerPro Designer".
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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Calypto's PowerPro Designer
We looked at Calypto's new "what if" exploration for design engineers.
It's a novel way of doing things.
We are designing a lot of new architectures. The impact on power is
greater at that early stage rather than later. However, we didn't
have a tool to work with designers at the early stage.
That is what Calypto's new power tool does. HW development is very
much like SW development. Our designers end up writing same code
for 28 nm as for 14 finFET. Yet the architectural specification
impacts how power is consumed.
The way PowerPro Designer works:
- Our designers write Verilog.
- Before we run the RTL through synthesis, PowerPro Designer
looks at structure and makes recommendations to reduce power.
- The tool highlights the area of interest, and even gives you
actual code to use if you want.
Each designer can use the new PowerPro Designer just as they all do
with logic synthesis. They don't have to have power expertise.
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Calypto PowerPro.
For its deep sequential analysis. Two ways of looking at power:
1. work on power reduction at the architectural level, or
2. work on legacy RTL post-architecture.
We used PowerPro on our post-architectural legacy RTL. We were almost
certain that we couldn't get valuable changes in a timely fashion.
This is because we've had most of the power reduction tools (Atrenta,
Synopsys, Apache) in house at some point over the past 15 years, with
only a 2-3% power reduction. So we assumed Calypto would be like
the others and fall short.
We were surprised that PowerPro reduced pre-silicon power consumption
by a full 15%. Further, it did so without forcing us to do anything
dramatic. The key is that Calypto:
- it uses deep sequential analysis to go into your implementation
details -- much deeper than SpyGlass Power or PowerArtist.
- it identifies pieces on the functional path that waste power
while doing nothing (e.g. clock gating at a different level.)
- it then gives suggestions that don't impact your functionality.
We did guided power optimization because the apps on our chips are
more complex and high speed; almost like a GPU. So we wanted to
see the impact of each change.
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We're about to standardize on PowerPro
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Calypto made a positive impression at DAC with PowerPro.
Samsung is using them, plus PowerPro's guided optimization is a
good improvement.
It's good they are focused on dynamic power. Dynamic power was
important at 65nm, but was set aside for leakage. With 16nm,
we must get dynamic power back in the front seat.
I've also seen PowerPro's GUI, looks useful for debugging power
problems.
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Calypto PowerPro's power analysis features make sense for RTL.
The guided manual mode seems to be a reasonable compromise, as
we have gotten a lot of push back from our design engineers who
do not feel comfortable having a tool changing their RTL codes.
SLEC Pro should have been part of PowerPro CG/MG by default.
If the tool is going to change the RTL, it better make sure the
new RTL is equivalent to the old one.
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PowerPro
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Calypto PowerPro is about planning for low power design during
RTL design. However, this doesn't impact our company as we
just do backend design.
---- ---- ---- ---- ---- ---- ----
Based on their DAC presentation, PowerPro looks just like how a
low power tool it should. However, I still need hands-on
experience to verify what it does.
---- ---- ---- ---- ---- ---- ----
Calypto PowerPro
---- ---- ---- ---- ---- ---- ----
I liked the way Calypto PowerPro went straight to the concept.
They also induced good ideas, like a useful classroom.
Especially the points about timing.
---- ---- ---- ---- ---- ---- ----
Calypto PowerPro:
- Dynamic power optimization in the FinFET arena
- "What If" scenarios
- power exploration for RTL design engineers
- deep sequential analysis
- moving power optimization to block level
---- ---- ---- ---- ---- ---- ----
PowerPro for guided RTL power reduction.
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ANSYS APACHE POWERARTIST COMMENTS:
I'm from power team so I'm primarily interested in tools related
to that.
Ansys PowerArtist -- it teamed up with Mentor Veloce 2 Power App.
It measures power while running emulation, running long test
sequences, isolating areas of high switching activity, significant
runtime improvement
---- ---- ---- ---- ---- ---- ----
We're bringing in the Veloce people to discuss Power App.
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Ansys Power App -
If this 4.5x faster runtime is true, we need it.
---- ---- ---- ---- ---- ---- ----
Veloce Apache Power App
---- ---- ---- ---- ---- ---- ----
Apache Power App
The ability to track power use with early RTL during a full
OS boot is very useful.
---- ---- ---- ---- ---- ---- ----
PowerArtist to estimate RTL power and CGR (Clock Gating Rate).
I like its reduction guide for non-gated flop and power debug.
---- ---- ---- ---- ---- ---- ----
PowerArtist
It gets an accurate power number for both RTL and gate level.
Like PACE as well as RPM and RTL power accuracy
---- ---- ---- ---- ---- ---- ----
We are using PowerArtist for power regression.
---- ---- ---- ---- ---- ---- ----
Since PowerArtist has a higher accuracy than Atrenta or Apache,
we use it for RTL power estimation and reduction.
PowerArtist's RTL power estimates are within 10% of our final
power that we've measured in silicon.
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GOOD: PowerArtist is good for RTL power analysis and optimization.
It supports mixed-language (Verilog, SystemVerilog, and VHDL).
with good inference and simulation annotation.
It's regressable, we can generate power rollups quickly.
Reasonably accurate power estimation.
Better tool stability.
NOT GOOD: Ansys PowerArtist lacks formal verification. It can not
verify its power-optimized RTL against the original RTL.
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ATRENTA SPYGLASS POWER COMMENTS:
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DOCEA COMMENTS:
b. Docea's power and thermal tools -- for fast what-ifs and
power-performance tradeoffs.
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