( DAC'15 Item 3 ) ----------------------------------------------- [11/05/15]
Subject: Cadence Innovus and Mentor Olympus-SoC #3 hot tools at DAC'15
IT'S ALL ABOUT THE NODES: Last August onward I interviewed 5 PD engineers
about PnR tools, one of whom was a foundry guy. Foundry guy reported:
Looking at my customer status chart, for sub 28nm, roughly 60% are
on Innovus in some way.
- 30% are pure ICC/ICC2/PrimeTime
- 30% mix ICC/ICC2/PrimeTime with Innovus/Tempus
- 30% are pure Innovus/Tempus
- 15% use Atoptech or Olympus-SoC with PrimeTime
ICC/ICC2 users use PrimeTime. Innovus users use mostly Tempus with
some PrimeTime. Not one customer uses Tempus with ICC/ICC2.
- from http://www.deepchip.com/items/0552-06.html
Note how PnR and STA are welded together. And how most design houses use
at least two layout tools such that 60% use ICC/ICC2 and 60% use Innovus.
What caught me off guard was the node breakout. At 28nm ICC dominates with
old Cadence EDI, Mentor Olympus-SoC, and Atoptech each doing well. Each
holding their grounds. Each getting good 28nm PnR results. What messed
with me is how these 5 PnR engineers saw 16/14nm and 10nm -- there, these
guys saw Innovus as gaining ground.
ICC2 stalls on 10nm. With coloring, congestion comes up. The ICC2
router sees the DRC violations. It fixes them and creates 2 more
problems. It fixes those 2 problems to create 4 more problems.
ICC2 ICV catches all of this, but ICC2 can't fix it.
Innovus has color-aware placement and color-aware routing. It uses
color from the beginning. ICC2 doesn't do color placement. They
just put DRC rules in to make sure cell coloring is clean. For 10nm
coloring is critical. Synopsys tells us they've taken care of it,
but we have no way to be sure. 20 and 16 and 14 didn't have coloring
as manditory. Calibre would just fix it. Calibre can fix color
issues there. But at 10nm color-aware PnR is manditory. This is
why we've swung 60% to Innovus.
- from http://www.deepchip.com/items/0552-06.html
For the record, these responses below are from users reacting to what they
saw at DAC'15. I didn't ask these chip designers about what node they were
working at, nor about coloring, nor about multi-patterning.
AART HAS A PATCH: The other thing you might notice in these ICC2 comments
below is many comments on how ICC2 is broken. Again, these comments were
from the June-July DAC'15 time frame. In around late August, Aart's people
have quietly put out a limited release patch version of ICC2. I do not
know if this patch works or not. If it does, a good number of SNPS users
will be very happy.
TOLD YA SO!: A full month before DAC'15, I broke in ESNUG 550 #4 that the
Mentor Sierra Olympus-SoC guys where working on "Project Nitro" as a direct
response to Aart's ICC2 & Anirudh's "Project Novus" pushes. Exactly as I
predicted, Nitro Olympus has a bunch of new rewritten code plus they're
yapping up hooks into their Oasys Realtime Designer quickie synthesis ala
floorplanner -- with Nvidia, Qualcomm, and MediaTek backing. I told ya so!!
From the DAC comments, CDNS Innovus and MENT "Nitro" Olympus-SoC had the
most traction with the users.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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Cadence Innovus
We will be evaluating Cadence Innovus digital flow soon.
Innovus has some strong customer endorsements: Renesas, Spreadtrum,
TI, Freescale. They had tons of benchmarks for production CPUs and
SoCs showing:
- Good PPA results across different design types and process nodes
- Overall thru-put numbers of 5X TAT
Cadence's claims that I like:
- The Innovus full digital flow has a common timer and extraction.
Cadence claims Genus will take advantage of them too, i.e. that
Genus + Innovus + Tempus will deliver best PPA in the industry.
- The digital tools combo have a common data model (to help with
design closure).
I need to see proof, but we'd be crazy not to check it out... if the
claims are in the ballpark, it would give us a advantage.
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Innovus Place & Route:
Based on our internal observation, Innovus has:
- Impressive speed improvements
- Better PPA with default out-of-the-box settings
- The expected TAT benefits for the integrated Tempus and Quantus
signoff engines
- The scalability to large blocks has definitely improved over EDI
My overall impression is positive, based on the observed run-time,
PPA benefits. I have no personal experience with their production
tapeouts and silicon measurements to date, but am cautiously
optimistic.
---- ---- ---- ---- ---- ---- ----
Cadence Innovus P&R.
I heard the run time gain is ~10x, which is very impressive.
So I'm wondering what technique has been employed - the code has more
parallelism or the algorithm has some breakthrough.
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Cadence Innovus --
I haven't used Innovus yet, but I plan to in the future. Cadence
claims faster turnaround time. I believe this is possible due to
massive parallel computing.
---- ---- ---- ---- ---- ---- ----
We just adopted Cadence Innovus, and are still trying to explore.
---- ---- ---- ---- ---- ---- ----
2) Cadence/Anirudh. Ex-Magma guys. Looks like their vision is
finally becoming production worthy. Will be interesting if
they can make a PnR which wins on QOR and not price bundling,
and if they can deploy it without the army of AEs that they
are famous for.
---- ---- ---- ---- ---- ---- ----
Cadence Innovus Place & Route
We used to use Cadence EDI and now have Cadence Innovus.
The biggest improvement we've noticed with Innovus is the new clock
tree engine "CCopt". Our analysis is that it's doing a better job
at reducing the depth of the clock tree. This will make timing
analysis easier and hopefully reduce power.
We don't have a license to check out the Innovus parallel processing
performance improvements yet.
---- ---- ---- ---- ---- ---- ----
I spoke to Cadence about the updates included in Innovus at DAC 2015.
The changes in Innovus have been gradually appearing over recent
releases of EDI, so we have already seen improvements in runtime
and quality.
The new updates should help reduce our runtime further and allow
us to effectively close timing across more corners (and see fewer
surprises in final STA).
---- ---- ---- ---- ---- ---- ----
Innovus Place & Route
We've been using Innovus PnR and have seen better turnaround time
than EDI; we've not been able to quantify the PPA benefits.
Innovus correlation to signoff (e.g. Tempus, Quantus) is "good
enough". At the end of the day the ECO capabilities in Tempus
for "last mile closure" are pretty strong.
Cadence continue to make incremental steps toward improving user
experience in tools. Innovus feels like a rebranding of EDI.
---- ---- ---- ---- ---- ---- ----
1: Cadence's new digital implementation tools (Genus/Innovus)
2: Jasper formal verification, and
3: Mentor's (Oasys) RealTime synthesis.
RealTime has interesting runtime and capacity but
drawback is that it is just qualified against
not-so-great Mentor Olympus P&R tool.
---- ---- ---- ---- ---- ---- ----
1. Cadence *us products (Innovus specifically). The introduction
of competitive landscape in digital/signoff tools has breathed
new life into EDA and the advanced node semiconductor market.
---- ---- ---- ---- ---- ---- ----
VCS, SpyGlass, Verdi3, DC-Ultra, PT, Innovus/EDI, Star-RC, Tessent
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MENTOR OLYMPUS COMMENTS
I attended the Mentor Nitro PnR suite session and the customer
presentations/testimonials. I also got to hear other users share
their experiences, design flows and talk about the tools.
Qualcomm presented on the Advanced Node Design Flow including
requirements for FinFETs and double patterning. They talked about
using Olympus on their wireless chip tapeouts. Also talked on
getting 8% power optimization, which I thought was impressive.
In the same vein, I also attend Nvidia's presentation. Nvidia
used Olympus power optimization on their graphic processors and
got 7% better power on top of the best optimized netlist.
Mediatek presented on Realtime Designer RTL floorplanning and
how it helped reduce 80% their frontend-to-backend iterations.
---- ---- ---- ---- ---- ---- ----
Mentor Olympus (Nitro)
Things I liked:
Speed - Instead of raw runtime comparison they were talking about
throughput. they can do 2 million instances in 24 hours. They
also claimed that Nitro was 5x faster than the previous generation.
Nitro seems be a complete overhaul of their old system including
a new placement engine, CTS, optimization, router etc and the full
flow utilizing parallelization hardware. They have also completely
redone the flow scripts. The comparison matrix highlighted almost
15 line items that were either complete re-writes or upgrades that
account for the speedup claim.
Power - Nitro uses Veloce emulation to generate accurate stimulus
for power analysis and drives all the optimization decisions.
Mentor claims an additional 10% reduction in power on top of the
best optimized netlist. Nvidia presented the Nitro power reduction
flow on their designs at 16FF and they were able to reduce power by
an average of 7%. Nvidia emphasized that this was on top of their
best optimized netlist.
Integration with Calibre - Integrating physical verification with
place and route has been a unique advantage for Mentor. They said
to have further bolstered with support for 20/14/10nm, FinFETs and
double patterning. Claim they've reduced ECO cycles "from weeks
to days" during the physical verification
Other - new optimization engine, area reduction (up to 10%) and
working on detailed FinFET/multi-patterning flows.
---- ---- ---- ---- ---- ---- ----
I attended the Mentor Nitro P&R session at DAC.
It focused on reducing project cycle time at 16/14nm and that the
new Nitro Olympus runtime is 5x faster than previous generation
and can throughput 2 million instances in 24 hours for PnR.
Nitro Olympus seems to be a complete rewrite of all the key engines
including placer, optimizer, router and the database. They have
also completely overhauled the flow scripts. Now multi-processing
and multi-threading for placement, opt, routing and CTS. The
throughput is 2M instances in a day; which matches our block size.
Other Nitro Olympus claims:
- emulation based power analysis with 10% additional power
reduction on top of best known methods.
- 10% reduction in area and die size.
- abutted floorplanning flow and area recovery technologies
and cycle opt for optimization that supposedly does
concurrent opt between placement, CTS, etc.
The other big benefit we see Nitro has is 16/14/10nm readiness
with its direct interface to Calibre -- the tool is able to run
Calibre DRC/DP/DFM checks and automatically fix the violations.
The customer presentations from Qualcomm (FinFET/double-pattern
aware design flow & power reduction) and Nvidia (power reduction
flow) backed their claims. Both Qualcomm and Nvidia reported
7-8% reduction in power on their design.
Nitro seems to be a direct response to SNPS ICC2 and CDNS Innovus.
---- ---- ---- ---- ---- ---- ----
I liked both Olympus Nitro & PrimeTime-SIG
---- ---- ---- ---- ---- ---- ----
Attended both Mentor Oasys RTL synthesis and Nitro place and route.
Nitro is their next generation place and route. It's much faster
than previous rev and complements their Oasys RTL synthesis.
Definitely a viable alternative to Synopsys and Cadence.
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ATOPTECH COMMENTS
Atop does the job fairly painlessly for us.
---- ---- ---- ---- ---- ---- ----
I liked:
a. Cadence Innovus
b. Synopsys ICC2
Both companies showed impressive results.
But we're an Atoptech house. We've found ATOP was better for 28nm.
---- ---- ---- ---- ---- ---- ----
Use ATOP exactly like Magma. Feed it blocks. 9 out of 10 are no
problem. On the few the Aprisia does not like we feed to ICC.
Once ICC2 is working, we'll them feed to it. We like ATOP as a
workload reducer. ICC/ICC2 blocks require a lot of handling.
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IC COMPILER II COMMENTS
ICC2 is 3X faster than ICC. It's the QoR that has to catch up.
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Synopsys IC Compiler II
Aart has a game changing winner here.
---- ---- ---- ---- ---- ---- ----
ICC2 is good when it works. PITA when I have to redo in ICC.
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We only have ICC.
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We're so invested into SNPS we're just going to wait out for
them to get the bugs out of ICC2.
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3. Biggest lie: ICC2. Not really the "worst", but I'd say
that Aart's technical marketing was caught sleeping.
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