( DAC'15 Item 1 ) ----------------------------------------------- [11/05/15]
Subject: IC Manage Tapeout Predictor beats Indago as #1 tool at DAC'15
MOUNTAINS OF DATA: It's like watching that new TV show "Limitless" where
the guy takes a smart pill and he can remember everything he's ever seen,
read, or heard -- and he can apply that info to the problems he's facing
now. THAT'S WHAT BIG DATA IS!
By far, the #1 tool at DAC this year was the IC Manage Tapeout Predictor.
Read the comments. The engineers were impressed. It takes a bird's eye
view of your entire company (both past and present) and using realtime
progress analytics you can hone in on the bottlenecks (which could be
man-hours, EDA licenses, "stalled engineers", or combo of all three) and
like Google maps -- you can zoom in on exactly what you need to see.
It's not just tweaking a design; it's a new tool that's tweaking the whole
design process. And that got this year's DAC attendees attention!
In a similar but more limited vein, CDNS Indago got some of this "Big Data"
shine because it does data mining on Verilog verification runs to predict
where other possible flaws in your chip are that one should look into.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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The IC Manage Envision "Big Data" tool for tapeout prediction.
We are sitting on mountains of data and not using it - any tool that
can help us to use it is interesting to us.
We've set a follow-up demo to find out more.
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We already use IC Manage GDP for design management. Their Envision
design tapeout predictor was interesting. It would be useful for a
project manager to correlate with the project schedule and closely
monitor the overall design progress.
Envision would also give us insights into man-hours and resource
bottlenecks through its ability to process all manner of log files.
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IC Manage Envision looks interesting.
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IC Manage Envision Tapeout Prediction.
It would give my team a level of confidence for tapeout convergence.
Larger companies would have a lot of data to draw from for Envision
tapeout prediction -- based on check-in/check-out and log data.
However, smaller companies have less data for predictions, so it
would be nice to have some models based on accumulated data from all
companies. Perhaps this is possible if the data is anonymized.
In the Xilinx presentation on Envision, they talked about how they
could drill down into the tool log data after one project ended, to
see that another was stuck. I think that makes a lot of sense.
I am curious how Envision handles active vs. passive tool usage; for
example, an engineer running P&R using a script, while at the same
time doing something else.
The Envision IP progress heat map is good as it would be pretty easy
to quantify. It would be useful if we could also to track if an IP
progress went backwards -- for example if the designer had to go back
to RTL synthesis after starting place and route.
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I saw a demo of the IC Manage Envision tapeout predictor. It looks
like a good tool for managing projects. It seems flexible, allowing
you to define the data you want to collect about each project, and
then define how you want to analyze data across projects.
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IC Manage is a very good first attempt at EDA data mining.
The tool analyzes the data signatures of how engineer's design data
access to learn/forecast useful schedul roadblock information.
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I talked to IC Manage at DAC about Envision (no hands on experience).
Their tool has potential to improve time-to-market by:
- Capture/manage engineering effort to better converge on
tasks such as timing, LVS, DRC clean up
- Create agile type workflow for chip design teams
Personally, I would like to see industry collaboration on data sharing
towards better analytics on TTM and benefit for all (ala Glassdoor for
tapeout predictions).
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IC Manage Tapeout Predictor is an interesting product, and something
needed in chip design.
Its individual tool analytics for resource optimization is good. The
license use info would be particularly informative, as those are big
decisions that we have to make year to year, and we get spikes during
tapeout for EDA licenses.
Tapeout prediction by comparing a current design to a past design
would be handy, but I would need to see that it's accurate.
Design progress analysis based on engineering tool check-in/check-out
and log files seems particularly useful.
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I was impressed by Envision - it's a tremendous step towards big data
analysis of design data.
The ability to filter data by tool/design is a very positive feature
for EDA license and GENERAL engineering staff optimization.
I don't like the part where it monitors a design enginner's specific
EDa tool check-in/check-out. Tapeout prediction is a very positive,
as long as it is not specific to individuals for tapeout schedule
prediction.
As for the Envision IP progress heat map, I would need a real-life
example to weigh the benefit.
Overall I like big data coming to chip design.
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IC Manage Envision Big Data.
1. Real-time design progress analytics - helpful.
2. Tool drilldown analytics for resource optimization - would be
nice to have.
3. Ability to do tapeout prediction and resource adjustments
for a project after completing one earlier project - would
be very useful.
4. SoC/Chip real-time IP progress, with a real-time heat map of
detailed IP progress - would be very good to have, as long
as it can integrate all contributions.
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Based on the demo shown at DAC, Envision looked interesting.
Our company has internal SW to solve many of the problems that
Envision tries to solve (specifically the metrics regarding
the pace of changes with respect to progress towards milestones).
But Envision is more refined, such that I can see it being used
by senior/executive management as a measuring stick to compare
against team forecasts for completing major milestones.
I'm looking forward to evaluating the tool further.
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IC manage Envision caught my attention.
It collects various metrics of your ASIC project to predict how
close you are to tapeout. I'm not sure how good the prediction
would be, but it's definitely useful for keeping track of
schedule/design issues and resource bottlenecks.
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IC Manage Envision
Big data and analytics on EDA tool-generated files and resources is
a long time coming feature that every CAD design engineer tries to
hack and put together in a very ad-hoc way. Typically these systems
need a bit more hacking again when project node or revisions happen
so they don't scale very well.
Adding viable big data design progress analytics can be a dream come
true for upper management.
- Tape-Out Prediction. I can see how this could be an added value
in predicting relative resources required based on prior designs.
"Relative" is the key word here. For new projects starting out on
a new process node predictions might be useful but for revisions
on a previous project, not sure how it would work because the
resources required depend on the extent of the change in the
revision and level of experience (it's not always the case that
previous engineers do revisions on existing designs).
- Design & IP Progress analytics. This is a good feature in most
cases. Right now what we have at my current job is a Git repo
that everybody pushes to and progress is typically reported on
a weekly basis in meetings - it is certainly tracked.
For a hands-on technical manager a Git repository should provide
a good enough insight. Envision's real-time progress analytics
may be overkill for a single design small team.
- Tool Drilldown / Resource Optimization. This is typically what
"infrastructure side" CAD teams automate with scripts and publish
on intranet. Some companies I've worked at have done this so
efficiently to measure: memory allocation, number of CPU's for
certain groups, certain tools and at what time of the day they
can be used, etc. in all possible combinations. The only thing
they did not do was monitor individual engineering staff data
because of the understandable personnel uproar it would cause.
I also think Envision might be far more practical for digital flows
than for analog IP. Its "real-time IP progress heat map" image
looks almost identical to the one we had at my old job. At the
time we tracked all progress of sub-blocks of a large SoC with a
system like this one.
Even if Envision's predictions are marginally accurate, it will be
better than yet another manager saying "we're almost there".
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IC Manage Tapeout prediction.
It's powerful to analyze where and how the resources are allocated
and used during any design phases, with the possibility to be able
to forecast future designs.
What I personally don't like is the possibility to look at who is
doing what and indeed the real-time spent by a specific person for
any task - "Orwell 1984". So powerful but dangerous in the bad
management hands.
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IC Manage Envision.
I saw a quick demo. Seems to me that tool is a bit immature at this
point. I was disappointed.
The exhibitor mentioned that they plan to include parses of various
important logs as part of the software release at some point in the
future. However, right now the user has to write report parsers for
various logs (like Synopsys DC logs, PrimeTime logs etc.) and gather
the data and submit it to IC Manage.
Envision does come bundled with the ability to work in conjunction
with version control systems and present things such as who made what
changes to which files when and why. I don't know why a separate
tool is needed for that, because all version control systems offer
that information.
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IC Manage Envision is a good first attempt at "Big Data Analytics".
- Their tapeout prediction, based on comparing relative resources
versus prior design to make resource adjustments, is valuable.
This is similar to the notion of "evidence-based scheduling"
enforced by some bug tracking tools.
- They also have 'real-time design progress' analytics based on time
delta between designer check out & check in, which is valuable.
The ability to leverage those analytics hinges on how disciplined
the entire organization is in terms of check-in and check-out
tempo.
- Envision's design progress and prediction features will work
better for mid-sized companies, or for companies that work in
a unified way, single revision control system and bug tracking
system etc. I believe some customers could develop these
functions on their own using 3rd-party foundation tools.
Overall, IC Manage is taking a step in the right direction here.
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I see value in IC Manage's tapeout prediction, particularly after
building up some history. I'm not sure how one accounts for the
time required for re-use vs. new designs, though.
My own team doesn't need Envision just yet, however, my company has
a variety of design teams that may better be able to leverage it.
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b. I had a lengthy discussion with the IC Manage team. It quickly
became apparent that we're sitting on a mountain of data that
we don't use effectively. All our Subversion repository info
can be mined and used to better understand development progress.
Also due to how we manage chip designs, we have an elaborate and
convoluted methodology to track bug origin and genealogy.
IC Manage would help us tremendously in this area and is very
important for any company with a large IP portfolio. We didn't
get beyond marketing presentations after DAC because we just
don't have the budget for a tool like IC Manage even thought it
would help streamline development.
The biggest challenge to using IC Manage is their reliance (cost
and features) on Perforce although they stated they can run with
Subversion but with some limitations.
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Biggest lie? That the IC Manage Big Data tool could help users even
if they do not use their other tools. We wasted a whole hour looking
at the demo, only to have the person not be able to tell us what data
outside their tool information would be useful.
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"Big Data" is getting lots of hype, though it means very different
things to different companies. IC Manage has been touting this for
a while, and since their tool sits at the point where design data
goes in and out of configuration management, they can collect useful
data for analysis and projection.
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CADENCE INDAGO COMMENTS
We liked the Big Data aspects inside Indago. It's a cleaver approach
to design debugging.
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I can't believe Cadence actually developed a tool that reduces the
number of Incisive runs (and therefore licenses) a customers uses.
How did that first internal Indago R&D proposal go exactly?
I want to know how whoever did this pulled it off.
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CDNS Indago
We want to see if it's compatible with Verdi first, as a temporary
transition. Later possibly go fully Indago. Our CAD group gets
all gushy about predictive debug and data mining.
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I wouldn't call Indago "Big Data". It's more like data mining.
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My management wants us to look at Indago deeper.
It might find issues that we're not catching.
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Indago
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Cadence Indago
It was announced at DAC. We have been using some of the components
for year now, so I do not know if it counts. It really helps for
debugging.
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Big Data Indago
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CDNS Indigo
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The Cadence Indago talk at DAC gave the impression that it worked
only inside an all-Cadence flow with Cadence only VIP. We didn't
think that was practical because we want to mix VIP specifically
because they're from different vendors.
Big Data doesn't work if all the verification data comes from one
source. Heterogenous verification of standard protocals is best.
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My spell checker says it's Indigo.
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Can Indago run with VCS and Questa logs?
What about Veloce or Zebu logs?
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Related Articles
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Dean Drako warns "Big Data" analytics coming for chip design DM
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