( DAC'14 Item 9 ) ----------------------------------------------- [12/18/14]
Subject: Calyto PowerPro, Atrenta SpyGlass Power, Ansys Apache PowerArtist
AND THEN THERE WERE TWO: Two years there was a very public threeway battle
between Apache PowerArtist, Atrenta Spyglass Power, and Calypto PowerPro in
RTL power optimization. See #1 in my Cheesy Must See List for DAC'12.
Last year at DAC'13 users stopped noticing Apache PowerArtist.
And this year history repeats itself with survey responders either talking
about Calypto PowerPro, or Atrenta Spyglass Power, or both -- with not one
engineer citing Apache PowerArtist as their "Best of DAC'14" tool.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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I recently evaluated Calypto PowerPro (RTL power reduction).
PowerPro's ability to do deep sequential analysis as part of power
optimization is what interested us in it.
Design Compiler does a pretty good job of power-gating within one
cycle. Also, our designers are pretty good at figuring it out
within a cycle. But both miss power opto across multi cycles.
I primarily tested their guided RTL power optimization on an ARM
sub-block. I used an existing block that was well characterized.
Power reduction: 10-20%
Estimated time savings vs manual: weeks
A lot of the reduction was from clock-gating for low performance
configuration buses.
PowerPro's "guided optimization" is fairly automated in that it gives
you a proposed change, but also gives you control in that you can
weaken the condition in case something is timing critical.
For example, if you have a clock-gate and want to turn it on or off
to save power, PowerPro says "here's what I found" and you can pick
portions of the expressions that you don't want to use -- such as
if you don't need to clock a flop if A, B or C are happening.
Calypto also has a good UI for PowerPro to let you explore where the
power consumptions and savings are. They do a nice job of results
visualization. You can select or deselect different items to see
what's going on.
You can also slice the data, with different filtering and orderings to
calculate the power for part of your design, or just display the flops.
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Calypto PowerPro looked good. It was a more complete tool and they had
more details in their presentation than Atrenta or Apache had.
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Calypto PowerPro - may be worth trying in our early stages of design.
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From the DAC meeting, here is what I gathered about Calypto PowerPro.
(I have not used the tool, nor has it been used in my group.)
- PowerPro is a RTL power optimization; input and output is both RTL
- It provides sequential clock gating, both guided manual or fully
automatic modes. Not available with Apache nor SpyGlass Power.
- Claims up to 60% power improvement
It's an interesting technology, but for our use the PowerPro automatic
mode is not useful, as we develop our own RTL and we insert clock-gating
logic manually.
Calypto claimed 60% power improvement from comparing a design with no
clock-gating. Real world case would be more of 10% or so improvement.
From the DAC presentation, we have not seen the possibility to improve
our current flow using Calypto.
Another very important aspect of doing power optimization at RTL is the
correlation to final physical implementation. I thought Calypto was
not very strong in this area, i.e., you can improve the design at RTL
relatively, but it is not clear how much power improvement that will
correspond post P&R.
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Calypto PowerPro - Nice features and solid presentation.
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Calypto PowerPro tool looked similar to Atrenta based SpyGlass Power in
our DAC session.
We are starting a new chip. Will look at Calypto, Atrenta, and Apache
in that order.
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Atrenta SpyGlass Power, Calypto PowerPro.
They both do complete power/what-if analysis, low-power recommendations
and formal verification to verify power-optimized RTL against the
original RTL. Ansys PowerArtist lacks of formal verification.
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SpyGlass Power by Atrenta.
We evaluated the tool about 2 years ago and were very happy to see
this time a lot of our suggestions were implemented in the latest
version of the tool like automated power profiling, power regressions,
memory power reductions, TCL scripting and the PowerExplorer GUI.
I like working with small EDA start-ups. They actually listen!
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The existing SpyGlass Power Estimation helps us tracking the
power footprint of our ASICs against the budget.
Being able to monitor activity, memory accesses and clock gating
efficiency per blocks and clock domain has proven very useful.
At DAC, Atrenta introduced a new power exploration framework and
new power reduction techniques that go beyond Calypto sequential
power optimizations.
We're interested in seeing if it actually works. Especially with
coarse grain clock gating.
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Atrenta Spyglass Power tool is getting a lot better now.
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Looks like the finally debugged Spyglass Power.
I was wondering when Ajoy was going to clean that tool up.
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Related Articles
User gets 37% Calypto PowerPro RTL sequential logic power savings
Spyglass Power for both architectural and RTL power reduction
Apache PowerArtist vs. post-Talus layout PrimeTime-PX correlation
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