( DAC'14 Item 2 ) ----------------------------------------------- [12/05/14]
Subject: Cadence EDI-Novus and MENT Olympus-SoC #2 hot tools at DAC'14
HELLO EDI NOVUS: In digital P&R, this year started with a fun surprise with
my 4 day SCOOP on Aart de Geus's SNUG'14 keynote being on "Project Newton"
a.k.a IC Compiler II. (ESNUG 537 #10) I snagged detailed info on ICC2's
new placer, new onion-layered data model, new MCMM timer, new internal
optimizer, old CTS, and old Z-Route. Sweet!
And for a second SCOOP, exactly 10 days before DAC'14, DeepChip also broke
the Cadence "Project Novus" story in ESNUG 541 #5 on what CDNS was secretly
telling its customers in response to Aart's ICC2! Double sweet!
Anirudh quietly tells users of "Project Novus" to nullify ICC II
http://www.deepchip.com/items/0538-01.html
So with all this build up, it was interesting to see how many engineers
cited Cadence Novus EDI as their "Best of DAC" tool PLUS how few of these
digital P&R users said anything whatsoever about ICC or Aart's ICC2.
  
MENTOR'S SMART MOVE: A lot of engineers also cited Olympus P&R plus the
Oasys RTL estimator as their "Best of DAC" tool. Two even likened it to
how the First Encounter RTL estimator had revived Cadence P&R.
And I had to chuckle when one engineer had called Atoptech the "fiesty
competition to ICC."
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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We're beta for Encounter Novus.
Novus runtimes compared with prior EDI versions are almost 3X.
It used to take 7-8 days in EDI flow from beginning to end,
now 2 days for 4 M instance design.
Further, we've seen tight timing correlation between the EDI Novus
internal timer and Primetime.
I'm excited for the next release with even more speed up.
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Novus is a collection of features like early prototyping, GigaOpt and
Tempus. It's not a standalone, newly written tool.
We are using this intensively and get really good results.
However for ICC 2 the situation is different. The 10X speed up over
ICC 1 is a little bit weird calculation for me. I guess that the main
reason for completely rewriting the ICC database is that after so many
mergers over the years it got uncontrollable especially looking at
14 FF -- so a complete cleanup was necessary.
But by the time ICC 2 achieves the "10 x ICC1" I guess that the others
(Novus, Atop, Olympus) will have passed this speed already (if not
already).
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Cadence EDI Novus -
We are very interested to see improvements such as layer assignments,
handling of complex DRC rules in 16ff -- i.e. whether the tools are
ready (as claimed) for 16 nm.
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It's a little early to say, but CDNS is projecting faster turnaround
time with Novus. That's the part that is the most interesting to us.
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Cadence made a mention at DAC that Novus will improve RTL-to-GDS
turnaround time with massive multi-threading in all tools.
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Cadence EDI-Novus.
Basically, they claim it's P&R for huge scale integration if it takes
you a lot of time -- over 5 days or more. So we welcome speed ups
of 10 times faster.
Of course not only speed but wiring quality including timing closure
is important.
We'll see.
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Cadence Novus is not a reaction to ICC 2. It's an internal clean-up.
Cadence's intention with EDI-Novus was to integrate their externsal
tool interface and common commands and internal interfaces -- like
Encounter, Voltus, Tempus, GigaOpt, Azuro CCopt, QRC, GigaPlace. It
creates better timing correlation vs. the current EDI version.
It is also to reduce the issues interfacing with multiple 3rd party
tools during any new feature additions -- which kind of require
changes across multiple CDNS tools.
I am not sure of the improvement in Power-Performance-Area, but it
will definitely bring design efficiency to help enable faster design
closure when using Cadence tools.
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At a high level, Novus felt less fleshed out than ICC 2 at DAC, in that
Synopsys was showing live demos of ICC 2, whereas Cadence was more
teasing the features of Novus.
I only draw that comparison since the general sense is that they are
both competing over the same idea of providing massive speedup.
In terms of what Cadence did discuss at DAC, the most impressive thing
that I saw was their demonstration of GigaOpt fixing timing failures
by re-working routing topologies -- which I have not seen anywhere
else so far.
Also impressive were the mentions that GigaPlace would become the
standard placement solution with Novus -- allowing for threaded
placement -- yet another thing that I haven't seen well implemented
anywhere yet.
Novus has a lot of promise. It will be interesting to see how well
it lives up to that.
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I used Cadence EDI in the past, and I found it to be straight forward
tool, user friendly. I liked its design browser where you can search
for things in your design and find them very fast and easily.
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CDNS buys First Encounter RTL estimator to beef up their digital P&R.
MENT buys Oasys to beef up Olympus. History repeats itself.
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The Oasys acquisition seems to be the right move for Mentor.
Oasys does "place first" methodology where all optimization is at the
physical RTL level rather than at gate-level. It reduces the number
of objects to be handled during synthesis resulting in 10x speedup and
100 M gate chip capacity. It was interesting to see placement info
and netlists of RTL partitions were used for timing and optimization.
Oasys is able to read a full chip RTL, synthesize the full chip, and
then partition the design, shape the partitions, place the macros and
also analyze congestion. Saves some back and forth iterations.
Their second demo was on cross probes between RTL and physical views.
The designer can cross probe between RTL, layout and timing views.
In the layout view yiu can switch between timing, congestion and power
maps -- neat stuff.
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I attended the Mentor RTL to GDS session at DAC that covered Oasys
Realtime and Olympus tools and also their customer sessions.
Power reduction is one of our key concerns. The Olympus dynamic power
reduction got my attention. Also activity driven placement, clock-
transition shaping, pin swapping and sizing that considers dynamic
power as a cost function were all interesting.
Claimed an average 5% reduction in dynamic power from PNR -- which
will be a huge plus for us if true.
Other likes:
- clock and data optimization from RTL stage (the demo
showed better timing numbers compared to gate level),
- resistance-based optimization,
- promotion of critical nets to higher metal for improving
performance.
- abutted floorplanning does Macro placement.
Both their customer presentations were on hierarchical floorplanning.
ST showed area savings with their abutted floorplanning flow compared
to channel based.
We like the idea of a Oasys/Olympus/Calibre flow. RTL estimation,
PNR, then run Calibre DRC checks to auto fix violations. Like.
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Mentor Oasys Realtime synthesis was definitely noteworthy. Optimize
at the RTL level as opposed to the gate level.
Other Oasys/Sierra stuff worth mentioning are RTL floorplanning, auto
PPA exploration and a single environment for physical and RTL views.
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We've done a number of Olympus SoC tapeouts. It's a good tool. Works
well and MENT gives us excellent support.
At DAC they talked up how Oasys Realtime would do super fast RTL-level
estimates similar to CDNS First Encounter. They claimed 100 M gate
capacity with 10X speeds faster than Synopsys Design Compiler.
We'll give it a look.
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Realtime Designer and Olympus seem to be very promising.
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Mentor Olympus P&R plus RealTime RTL synthesis.
RTL floor-planning placement, fast RTL syntheisis, single environment
debug. PNR does dynamic power and die size reduction.
Hope they deliver on the integrated RTL to P&R story.
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Mentor Oasys RTL Synthesis and Olympus P&R.
A possible alternative to Synopsys DC Explorer/ICC and
Cadence First Encounter/EDI.
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Oasys and Olympus
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Mentor Olympus. Has new Genesis Macro placement that seems to be
promising. Calibre InRoute for recommended rules, pattern matching,
antenna fixing etc. They are headed in the right direction.
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Mentor had some interesting things to say at DAC on their full
flow story and also had customer testimonials in their suite.
Oasys speedup claims continue and they were also pushing their
front end floorplanning in Olympus. With their RTL synthesis
they are going head to head against Synopsys ICC and Cadence EDI
for digital implementation.
Will have to wait and see on how they fair.
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Synopsys ICC2, Atoptech Aprisa, Primetime physical ECO.
I believe these tools could achieve order of magnitude improvement
in productivity or QOR -- if you believe their claims.
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Suspicious -
ICC2 10X speed improvement, still waiting to testdrive it.
But even within big companies, not everybody is switching to ICC2.
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Best tool - Atoptech, then EDI
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We like Atoptech. They're the fiesty competition to ICC.
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My compatriots at TSMC presently favour ATOP.
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Our group runs all of our design blocks through AtopTech first.
Aprisa is much like Magma Talus. It digests 90% of what you
feed it with no bother. The remaining 10% problem blocks we
have to babysit by hand through ICC.
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Related Articles
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