( DAC'13 Item 4 ) ----------------------------------------------- [09/27/13]
Subject: Berkeley DA ACE & AFS Mega, Solido variation were #4 at DAC'13
BEST PUBLICITY EVER: For the past decade, Berkeley DA was a small, unnoticed
start-up that quietly sold yet another SPICE simulator in a crowded market.
Nobody thought much of BDA back then. Then BDA started winning benchmarks
against CDNS. (See ESNUG 494 #9 & 495 #4.) Then in a public relations
blunder, Cadence kicked BDA out of the Cadence Connections program and then
CDNS sued BDA for "breach of contract" because BDA used SKILL instead of the
crippled OASIS interface into its ADE environment. It backfired horribly:
"So this whole veil of CDNS openness is not really truly open."
"I think this lawsuit is just sour grapes from a pissy Cadence."
"I think this lawsuit is just harassment by Cadence because they
are losing sales to BDA."
- from http://www.deepchip.com/items/0523-02.html
because it told customers that BDA sells a suite of tools that Cadence feels
threatened by -- i.e. these are tools that analog/full custom designers
should seriously look into buying! (D'oh!)
Now customers are writing in about BDA's new ACE and AFS Mega tools.
Following a similar vein, Solido has been holding its own in a very public
questioning by Lib Tech (ESNUG 513 #6), Cadence (ESNUG 524 #5), and MunEDA
(ESNUG 531 #6) of Solido's 6-sigma Monte Carlo claims.
Now the bulk of SPICE customers are writing in about Solido's variation as
their Best of DAC, while MunEDA gets only one honorable mention -- and
ProPlus, Infinisim, and Cadence variation had no customer fans. (D'oh! 2)
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
---- ---- ---- ---- ---- ---- ----
Berkeley's Analog Characterization Environment (ACE)
We had lots of issues with moving to the new Cadence 6 with ADE-L
set-up with all their changes. This caused a "doubt point" with
my management. "With all these ADE-L changes, wouldn't now be a
good time to see what else is around for characterization tools?"
The five main factors that convinced us to move to BDA ACE were:
- ability to thoroughly characterize any complex analog circuit
- effective performance vs. specification reporting tool
- ease of use shortening the overall setup time.
- costs of poorly characterized circuits
- yield
We like ACE's ease of use, self-explanatory menus and toolbars. It
lets our analog and mixed-signal designers quickly characterize their
circuits. ACE has an intuitive drag-and-drop based user interface to:
- Rapidly setup complex analog characterization runs.
- Help the user to launch, distribute, monitor and visually analyze
complete sets of corner and Monte Carlo (MC) characterization runs.
ACE gives us quick characterization capabilities with a reliable
understanding of how the circuit will perform in silicon.
---- ---- ---- ---- ---- ---- ----
Berkeley-DA's AFS Mega
We ran an evaluation of Berkeley-DA's AFS Mega simulator and are now
using it for production design at 28 nm.
AFS Mega is a high-capacity (100 M+ elements), fast and accurate SPICE
simulator for memories. It uses a SPICE engine instead of a digital
fastSPICE engine like FineSim Pro, so it does NOT make any of the
approximations -- like table look-up for models or event-driven-based
simulation. So it's even faster than FineSim Pro, as well as more
accurate. We looked at it because TSMC said they're supporting it.
BDA's AFS Mega is the first simulator we have seen that can handle the
extremely dense parasitic netlists that see coming out of extractors
at 28 nm (and below), which include interconnect parasitics. These
parasitic coupling capacitances are a significant portion of total
capacitance! They're a major headache for digital fastSPICE.
We also looked at Cadence XPS over this eval period. I'm not sure if
XPS has been announced yet; it is a digital fastSPICE type of tool.
It has high capacity like AFS Mega, but XPS' performance-accuracy
trade-offs are not sufficient for our SRAM characterization needs.
We need 2-3% timing accuracy and 5% or better current accuracy (for
our power sims) - and we cannot live with long turn-around-times.
That is not possible with XPS. And with digital fastSPICE, if you
need more accuracy you have to pay with slower speed.
AFS Mega's "default" mode results were well within our requirements.
AFS Mega is also fast. We could not understand how BDA was able to do
this until we realized that parasitic coupling capacitances are a
significant portion of total capacitance -- and these slow down the
traditional digital fastSPICE simulators. So there is something
fundamental changing with our designs, and we think the BDA guys
figured it out.
---- ---- ---- ---- ---- ---- ----
Solido Variation Designer
A suite of tools for statistical analysis of circuit variation. It's
GUI sets-up simulations, the general optimization, and the post-
processing analysis of the SPICE data.
It's useful in circuit optimization to reduce sensitivity to process
variation, and in the tuning of standard cell libraries.
---- ---- ---- ---- ---- ---- ----
Solido looks interesting. It handles variation issues, which are
having a bigger impact for scaled technology processes.
---- ---- ---- ---- ---- ---- ----
Solido Variation Designer for std cell/memory/analog IP
Optimization across 3-sigma MC and PVT variation
100x faster Monte-Carlo
2-50x faster PVT corner analysis
---- ---- ---- ---- ---- ---- ----
This DAC, Solido was kind of omnipresent. They had tutorials, booths,
presentations, discussions (in short - everything).
The tool (due to my doctoral background in variation-aware stuff)
that interested me is Solido's Variation Designer - a tool for PVT
variation-aware logic (standard cell) and memory (bit cell, sense
Amps...) characterization and optimization.
Since the feasibility of larger designs not evaluated, I found Solido
more suitable for analog/RF components. Nevertheless I was impressed
with their philosophy behind High Sigma Monte Carlo (HSMC), which is
to "reach worst case quickly, and then search around worst case to
derive that corner".
Though it normally requires billions of samples to achieve 6 sigma
confidence, it was interesting to see Solido get this with a few
thousand samples instead.
In my view, Solido's tools and 6-sigma approach are definitely
candidates worth exploring further.
---- ---- ---- ---- ---- ---- ----
I saw Solido at DAC; we use their Variation Designer tool in our
analog/RF group. We enjoy shorter simulation runs with Fast PVT and
Fast Monte Carlo while retaining high quality results. Brute force
simulation runs compute the entire problem space.
Through Fast Monte Carlo we are able to focus on the most sensitive
areas of our designs. This has allowed us to reduce the amount of
overdesign we have done in the past.
Fast PVT
Classically we would run SPICE simulations through the entire PVT
range using discrete values and then pick out the best- and worst-
case corners. This would be long and tedious.
Instead, Solido figures out which corners we need to simulate by
predicting the trajectory of each P, V, or T range. So with Solido
we can find our corners faster and iterate on our design faster.
We end up using the extra time to run more detailed analysis that we
wouldn't otherwise do and with more design confidence. Plus with
Solido we don't overdesign. We don't need to guard-band because we
already have accurate worst-case corners.
Fast Monte Carlo
Allows us find which devices have the most impact on performance,
i.e. which devices are most susceptible to variation.
With normal Monte Carlo analysis, all the factors for variation are
analyzed in a random fashion and can take thousands of SPICE runs.
Using predictive algorithms in Solido we are able to significantly
reduce the total number of simulations while still maintain a high
confidence in our results.
Solido Viewer
The simulation window gives you a view of total SPICE simulations,
current running simulations, and how far along the total job is.
As each SPICE run completes you can see the results in real-time.
The viewer is useful in giving insight into how well your design
is responding.
---- ---- ---- ---- ---- ---- ----
Solido has an impressive technical advantage in designing circuits
for 6 sigma variations. Their analysis is a viable commercial
alternative to our in-house custom tools.
---- ---- ---- ---- ---- ---- ----
Solido Design gave a good DAC presentation on Variation Designer.
I like the approach they demonstrated, it was fast and efficient
and is useful for predicting yield.
Having said this, I have not actually validated their tools yet.
---- ---- ---- ---- ---- ---- ----
We already use Solido Variation Designer. My purpose for the DAC
meeting was to pick the brains of the Solido experts to see what
cool features/capabilities/uses we may be not aware of. And, as
it turns out there are some.
They have tools for optimizing SPICE simulation efficiency to
target a desired statistical variation -- as well as general trend
analysis. It looks helpful to determine the characteristics of
your extreme outliers.
---- ---- ---- ---- ---- ---- ----
I attended a Solido presentation given by Trent McConaghy. I could
not help but be impressed by his grasp of the problems discussed and
get infected with his enthusiasm and energy.
I continued to be impressed at a follow-up demo at the Solido booth.
---- ---- ---- ---- ---- ---- ----
I looked at both Solido and MunEDA.
Solido. When it comes to pure variation-aware circuit design and SPICE
simulation, Solido seems to be better at it than MunEDA. Solido was a
more dry tool, displaying raw numbers and ASCII characters on the screen
for you to look at. Design engineers will take a "dry" tool that
solves their problem over a "user-friendly" tool that doesn't solve
their problem any day, so "dry" is not all bad -- it just depends on
what set of problems you are trying to solve. Same goes for "focused";
which Solido is: focus on one problem and do it well, good for users.
MunEDA. MunEDA takes on more EDA problems than just variation-aware
design -- such as schematic porting across technologies. MunEDA is
more user-friendly than Solido. Since our division's greater problem
is porting circuits across technologies (which is MunEDA) -- who happen
to also need variation-aware design -- I think MunEDA is the better
fit for us.
---- ---- ---- ---- ---- ---- ----
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