( DAC'13 Item 2 ) ----------------------------------------------- [09/27/13]
Subject: Jasper SEC & Datapath versus Atrenta BugScope were #2 at DAC'13
BUGHUNTERS: Looks like Jasper and Atrenta did quite well in bughunters this
year at DAC. The Jasper Security Path Verification App got mindshare from
those worried about tricky accidental data leaks in their on-chip networks,
and Atrenta BugScope got user kudos for automatically finding bug scenarios
that you didn't even know you had!
On the business side, the rumor mill went wild that Atrenta was going to
IPO this year (right before/after DAC actually) -- but it never happened.
SCOOP: It appears that Kathryn is going head-on against Calypto SLEC in the
sequential equivalence checking business! The new tool she demoed behind
closed doors was called "Jasper SEC". Is it Verilog/VHDL to Verilog/VHDL?
RTL to netlist? C/C++/SystemC to RTL??? Inquiring minds want to know!
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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Jasper SEC is a new Sequential Equivalence Checking (SEC) tool. As
other Jasper formal tools, the GUI is friendly to use and its engines
are highly tuned for SEC applications.
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1. Jasper formal apps
2. register automation tools (Semiforce, Duolog)
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Jasper Security Path Verification App (SPV)
The ability to determine whether data can propagate outside of secure
memory, even if data has been transformed or only portions of data is
able to leak out.
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I vote Jasper Secure Datapath stuff as BEST OF.
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I'm surprised that ARM or one of the NoC IP companies hasn't tried to
license the Jasper Secure Datapath Verification App. It's a natural
for what those IP companies sell.
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Jasper SPV -- our end buyers are paranoid about data leaks.
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Jasper Formal Architecture Validation:
Enables running of formal proofs when all you have is a spreadsheet.
Jasper also restructured the licensing model to make it easier to use
their proof kits.
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Mngmnt wants me to look into the Jasper Power App because verifying
a chip that's been all loosey-goosey power fixed is a nightmare. If
Kathryn's Formal Nerds have a guarenteed way to do this automatically,
my company will gladly throw money her way.
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JASPER
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BugScope from Atrenta
The best part of the tool is that you can run it once, sit back, and
let it tell you how your design coverage closure is going.
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1. Atrenta BugScope - promises to catch design corner cases that
dumb engineers can't/don't think of
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As a BugScope user, I enjoyed talking directly with the creator of
BugScope at DAC. He presented his direction for the tool in the
future. And I was able to give him feedback on how I benefit as a
user on the tool.
An indirect use is that it helps get logic designers into assertion
creation and analysis. Many of them needed a starting point in
assertion creation.
---- ---- ---- ---- ---- ---- ----
BugScope enabled us to find missing scenarios in our regression suite
after we our final release code and functional coverage goals.
---- ---- ---- ---- ---- ---- ----
I think Spyglass "cover coverage" goes well with BugScope formality.
---- ---- ---- ---- ---- ---- ----
BugScope assertion synthesis really makes assertion writing language
independent -- as assertions can be written in a graphical way,
almost like writing an equation!
Its GUI has controls and expressions ready for drag and drop. This
way our people don't need to be assertion experts in order to write
otherwise complicated assertions. Also once written, the assertion
can be compiled into any supported language.
On the downside, I can only think of whether people will choose using
BugScope or mastering their assertion coding; I think it will really
depend on how many assertions they need to develop. If there are
many then BugScope is a highly recommended tool. If there are few,
it should be cheaper just to hand-code them the old way.
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I have not used the Atrenta/NextOp BugScope tool, I have only seen
presentations and demos.
BugScope looks very interesting for developing high value emulation
compatible assertions. I have some concern over the number/size of
runs required to provide waveform input to the tool for it to do its
work.
Also there is concern about the overhead (capacity and performance)
impact BugScope will have on the emulation models.
I plan to evaluate the tool at some point in the future to get a true
picture of how well it works in a real SOC environment. If the
overhead is reasonable and the assertions are valuable and manageable,
then BugScope should prove to be valuable in the emulation context.
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BugScope seems like a useful tool on the surface - analyze implicit
design properties from the inside out! - but requires designers to
spend valuable time classifying assertions... essentially having
the designers help with verification.
It might be something worth looking into for new or understaffed
verification teams (and overstaffed design teams!) but it required
too much upkeep/maintenance/babysitting to prove useful for our team.
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Because most of our designers are too busy to write assertions, we are
interested in the property synthesis function that BugScope provides.
BugScope is good at generating properties between signals in the same
module. But there is a question about when is the right time to run
the property synthesis in the verification flow.
If you run it in early stage, when design or testbench is not mature
enough, many of the generated properties will be meaningless. Which
means our designers will take lots of time to review these properties
to get few useful properties. If you run it when the design and
testbench are both mature, the generated properties can't give you
too much help because the verification is almost done.
Atrenta is aware of this problem, and they introduced their unique
BugScope function (as I know), the "Progressive App". It helps to
solve the dilemma, and other property synthesis tools seem not
provide similar solutions.
But Bugscope has other problems to overcome: The property generation
runtime, and the density of the properties.
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BugScope.
It's clearly leading in automating coverage and inferring design
intent. That said, I view BugScope as an up-and-coming tool that
needs to continue becoming more powerful.
Specifically, I'm looking for more powerful artificial intelligence
that can infer complex relationships between 4 or more RTL signals.
The best part of BugScope is that it can be used in passive mode
with almost no active involvement. The user can set it up once,
and then simply use BugScope's coverage points as a proxy for
functional verification progress.
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Real Intent Ascent
Maybe someone has actually created a linting tool that is easy to use
and maintain. It's on our list of tools to evaluate.
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ZAZZ from Zocalo:
With incorrect System Verilog Assertions (SVAs), verification engineers
can waste a lot of simulation and debugging efforts. Writing concise
and efficient assertions requires a lot of experience. ZAZZ is the
only tool that I can find to debug assertions before running simulation.
Trek from Breker:
Graph-based constraint tool that can help to generate C based tests.
Improves verification coverage and catches design bugs in hard-to-hit
scenarios.
I strongly suggest DV engineers to check out both of these tools.
---- ---- ---- ---- ---- ---- ----
Questa AutoCheck - x-optimism checking in designs
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DVT by AMIQ
A good IDE is a must have for design and verification community. About
time we stopped writing code like it's 1976.
---- ---- ---- ---- ---- ---- ----
I like Amiq DVT Eclipse and Amiq Verissimo.
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