( DAC 12 Item 6 ) ----------------------------------------------- [09/20/12]
From: [ Graham Bell of Real Intent ]
Subject: Real Intent's DAC survey on CDC bugs, X propagation, constraints
Hi, John,
We had 318 surveys turned in at our DAC booth. Here are the results from
the ones that were filled out beyond just the contact info (duplicates and
"junk" forms were removed).
"When is your next design start?"
0-3 months : #################################################### (53%)
3-6 months : ############################# (29%)
6-12 months : ################### (18%)
My reaction to seeing over half of the future design starts occurring in the
next 3 months leads me to think design activity is not slowing down, but
in fact is remaining strong despite any uncertainty there might be in the
economy. Respondents were obviously at DAC to learn what is available to
solve their imminent design and verification problems.
"How many clock domains do you expect it will have?"
under 50 : ################################## (68%)
50-100 : ########## (20%)
100-500 : #### (8%)
over 500 : ## (4%)
We asked this question to find how many different asynchronous clocks need
to be analyzed with CDC verification tools. When we see designs with over
100 clocks they are typically mobile devices which use aggressive low-power
goals and use multiple-clock schemes to cut power. Designs with less than
50 clocks are often block-level designs such as Design IP, or for commodity
consumer electronic products.
"Have you seen CDC bugs resulted in late ECOs?"
Yes : ############################### (62%)
No : ################## (38%)
"Is CDC verification a sign-off criterion?"
Yes : #################################### (72%)
No : ############# (28%)
These two questions confirmed designers are suffering CDC bugs, which is
affecting their schedule and that they need to do CDC verification sign-off.
What are the other 28% doing? Some design teams tell us that their design
methodology is immune to CDC issues. We think this isn't typical for
fabless semi design teams.
"What verification technologies are you looking to adopt or change?"
CDC : ############ (25%)
automatic
formal checks : ########### (22%)
design constraint
analysis : ########### (22%)
X-propagation
analysis : ####### (14%)
lint : ######## (17%)
"What issues have you encountered with your current CDC or Lint tool?"
performance : ###################### (44%)
noisy reports : ############# (27%)
capacity : ############ (23%)
other : ### (6%)
I was not surprised tool performance is a strong #1 for CDC and Lint. We
often meet designers struggling with slow Lint and CDC tools.
"How concerned are you about differing X-Interpretation between
synthesis and verification causing functional bugs to slip through?"
Very Concerned : ################# (34%)
Moderately Concerned : ########################## (55%)
No Concern : ###### (12%)
"Please check off your X concerns:"
X-optimism : ############ (23%)
X-pessimism : ##### (11%)
We have a new tool for uncovering and mitigating X's in designs and wanted
to confirm the need for this. X-optimism in RTL can mask functional bugs
and X-pessimism can cause unnecessary X's at the netlist level. Almost 90%
of respondents were moderately or very concerned about X-issues, so we are
answering a real need with our product.
For SDC timing exceptions and constraints management,
what "pain points" exist for you?
Constraints Checking : ################# (34%)
Exception Generation : ########## (20%)
Exception Validation : ######### (18%)
Constraints Creation : ######### (18%)
EC between sets of
SDC constraints : ### (10%)
I was not surprised Constraints Checking is the main issue for SDC timing
constraints. What is a surprise is that 20% thought Exception Generation
was a pain point. In our experience, designers are often hesitant to use
Exception Generation since they do not have a way to sign-off on an
automatically created exception.
WHY I'M HAPPY
This survey showed CDC analysis is a sign-off criterion for most designs,
and that better verification is needed to stop CDC bugs causing late ECOs.
I'm pleased to let your readers know that my Meridian CDC is the answer! :)
Its structural and functional analysis ensures that signals crossing
asynchronous clock domains are received reliably in designs with 100 M gate
designs and over 100+ clocks.
The survey also highlights the need for better speed and low-noise reporting
for RTL Lint. Our Ascent Lint tool can process 25 M gates in 30 minutes.
Finally, I'm happy to have confirmed that our new Ascent XV product is the
remedy to concerns about both X-optimism in designer's RTL and X-pessimism
in designer's gate-level netlists.
- Graham Bell
Real Intent, Inc. Sunnyvale, CA
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