( DAC 12 Item 3 ) ----------------------------------------------- [09/20/12]
Subject: Berkeley AFS Memory Simulator, Solido PVT as #3 hot tool at DAC'12
SCOOP SCOOP SCOOP: Like this section because I got scoops on two BDA tools,
the unannounced Berkeley AFS Memory Simulator vs. SNPS FineSim plus a user
eval on new rev of BDA AFS. On the other side, I've heard that Solido sells
based on how many SPICE simulators it causes an designer to NOT buy! On
28/20/14 nm circuits that use 1,000's of SPICE runs for all those corners
at $10K to $25 K per SPICE license; that's serious $$$ millions in savings!
Anyway, these two Berkeley/Solido SPICE-related tools taken together were
the #3 most interesting tools users saw at this DAC'12.
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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DAC'12 NDA -- BDA AFS Memory Simulator
We evaluated the new Berkeley AFS Memory Simulator on a 28 nm
embedded CAM.
We now use both Magma/SNPS FineSim and the BDA AFS Memory Simulator,
though our usage of AFS for memory is more recent. We looked at this
new memory simulator in part because we had problems simulating the
whole memory (30 M transistors) in FineSim.
Finesim has two simulators, FineSim & FineSim-Pro. Their marketing
claims are that Finesim-Pro has more capacity and better simulation
speed but we have not adopted Finesim-pro, as we are not convinced
of its accuracy. So, comparing AFS Memory to FineSim, we noticed
that large extracts which were very slow or couldn't be simulated in
FineSim could be simulated with the AFS.
We adopted AFS Memory late in our verification cycle (close to tapeout
of the CAM) as a last measure, over-riding our previous methodology
using FineSim.
In the past, we did *not* use BDA standard AFS for memory simulations,
as it was not easily integrated into a memory flow. In comparison,
this new BDA memory simulator has hooks that make it fit easily into
our memory flow. (For example, it supports control/config options
and SPF files.) On critical path or full-macro SPICE runs, it has
same or better performance than Finesim and better accuracy.
We used to use HSPICE or Spectre as our golden simulator. However,
over the past year we trust BDA results stand alone, and use it as
"golden" against the class of "fast-simulators".
- [ An Anon Engineer ]
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BDA revamps AFS core simulator
I wanted to share my experience on the revamped BDA AFS core simulator.
We eval-ed it it, and also used it for production design.
We used the new AFS on some PLLs and high speed SERDES circuits. (We
used the older AFS simulator extensively for previous PLL and IO/SERDES
circuits.) Nodes spanned 65 nm down to 28 nm. Looking at 20 nm.
The new version of AFS is noteworthy based on its:
(i) faster speed,
(ii) lower noise floor,
(iii) multi-core parallel capability,
(iv) post-layout and top-level simulation capacity.
Specifically, it's:
- Approximately 2.5X to 3X faster.
- Post-layout simulation performance (for large
extracts) has improved by about 2X.
Also, the new AFS S-parameter fitting is better. It is easy to simulate
large numbers of corners with one corner per core.
We have taped out with the new AFS, though we don't have silicon back
yet. However, we have taped out multiple products using prior versions
of AFS, and its silicon accuracy is very good. For example, the phase
noise simulation for high fidelity PLL matched within 2 dBc/Hz of Si.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
For certain designs such as wireless, Cadence Spectre isn't enough.
We're seeing capacity limitations with it. So we use Berkeley AFS.
For instance, when it comes to RF transceivers, we have millions of
transistors and Spectre won't even run. BDA AFS is killer there.
A distributed dual-band LC VCO can take 2 weeks with SpectreRF, but
only 30 minutes to run with BDA.
For these designs our golden reference is always bench measurements
and we see good correlation in both CNDS and Berkeley simulators.
So it makes big difference from being able to run corners overnight,
versus only at sign-off. With this run time, BDA AFS also allows us
to use Solido to optimize our design and get higher yield.
We did not do that before and yield always suffered. We also had to
stick with costly fabs which kept our margins down.
- [ An Anon Engineer ]
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I saw Solido's Variation Designer at DAC. My interest is from an
analog and RF design standpoint.
We consume many thousands of Cadence Spectre simulators. We depend
on SPICE-level accuracy throughout the design process.
Solido PVT analysis. During day-to-day design, we only run 3-4
corners. During a design review, we probably run 100 corners.
Solido Variation Designer runs a sensitivity analysis based on
process and design parameters and narrows it down. Solido PVT
might take it down to 10 corners -- a 90% reduction -- it all
depends on the design.
Solido High Sigma Monte Carlo. Monte Carlo variation analysis is
a requirement for us, especially at 45 nm for RF and 0.25 um for
analog/power. You can try to do a brute force approach for
6 sigma design, but it will take 1 billion samples and not worth it.
Solido does Pareto and design of experiments analysis so you don't
have to run the full factorial number of simulations to get the
coverage. They start with experiments to identify the sensitivity
and to identify the relevant corners. They identify, based on
objective functions, to make sure you meet your yield from the fab
with fewer simulations.
A big Solido plus is that we can take an existing released product
and improve its performance (e.g., less power consumption, faster
performance, higher yield).
- [ An Anon Engineer ]
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My company bought analog IP recently which we then incorporated into a
product. During the integration and design improvement phase, our
circuit design reviews were not very uniform.
Depending on the analog designer's experience level we either got good
PVT/MC results or poor.
Our older designers already had Ocean scripts they used to automate
their SPICE runs, and used the results to optimize their circuits.
Our younger analog designers who were brought in to fill open design
positions did not know how to port these Ocean scripts, or how to
improve the design after running a corner SPICE simulations.
We will be porting this design to another process node next year and
our feeling is we are going to run into the same problem.
Solido's Variation Designer demo showed how a designer can gain insight
into their circuit and optimize it using their tool. Since everything
is graphical, learning how to use it should be fast. Also the work they
put into creating PVT tables can be reused. I was convinced enough to
commit to integrating it into our design flow later this year in
preparation for the IP port to the new process.
- [ An Anon Engineer ]
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I am a researcher working on mixed-signal design flow at my company.
Solido showed me their high-sigma Monte Carlo demo at their booth. It
might help yield estimation or yield analysis a lot especially in the
memory field.
It was very cool.
I feel Solido's tool can work well, if the input variation data is
accurate.
- [ An Anon Engineer ]
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Went through the Solido Analog+ demo. Pretty impressive about the
number of testbenches reduced and still got an accurate 3 sigma
results - claimed by Solido.
Overall their integration with Cadence is good. At least everything
worked pretty smoothly during demo.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
The addition of Memory, Standard Cell and Low Power design flows in
Solido Variation Designer was a big improvement from what they were
offering last year. They were from close collaboration with our
company's own designers to meet some of our advance design needs.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Solido gave a useful presentation. I was impressed by their material
on the effect of statistical variations on timing and yield.
Solido was responsive and seemed to understand my concerns well,
especially with regard to the type of information that we ultimately
use in our design process.
I was impressed that Variation Designer could do statistical timing.
- [ An Anon Engineer ]
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