( DAC 11 Item 11 ) ---------------------------------------------- [10/13/11]
Subject: Magma FineSim, Berkeley AFS, SNPS vs. LAVA SPICE Clouds, Solido
DON'T LOOK BEHIND THE CURTAIN: The worst kept secret in recent EDA news was
leaked in my pre-DAC Cheesy Must See list:
Rumor has it Samsung Memory and Samsung Logic both used to be 100%
Synopsys HSPICE/CustomSim/HSIM/NanoSim/XA houses until two benchmarks
caused Samsung Memory to go 100% and Samsung Logic to go 50% Magma
Finesim. That's an est new $15 M / year for 3 years going to LAVA!
Why? Magma's DAC write-up says it all: "Finesim's the only fast-SPICE
today that runs on multi-CPUs/multi-machines. One customer taped-out
a 1.5 M transistor design that ran on 8 CPUs in 4 days, and 1 day on
32 CPUs. Adding RF (harmonic balance) this year. In one benchmark
Finesim averaged 3X faster vs Synopsys XA, 3.2X faster vs Spectre APS.
In another, 6X faster vs HSPICE and Spectre couldn't run the design."
Toshiba, Hynix, Micron, Sandisk, IDT, TI, TSMC, Maxim, Melfas use it.
- from http://www.deepchip.com/gadfly/gad060211.html
Since DAC, more has unfolded on DeepChip about it:
Synopsys appears trying to counter the Samsung/Magma SPICE rumor
Magma financial calls confirm Synopsys SPICE is losing to FineSim
Rumors of Synopsys SPICE losing to Magma FineSim at Samsung
An interesting internal Synopsys slide; assuming that it exists
The latest rumor has it that SNPS has *dropped* their internal annual SPICE
sales quota from $130 million down to $60 million -- presumably due to sales
losses against Magma Finesim and Berkeley AFS. (Don't ask Aart. He doesn't
want to talk about it.)
I do have to compliment Aart for his Synopsys Cloud stunt; although nobody
on the Verilog/VHDL side cared for it, two SPICE users liked it. Perhaps
that's because an RTL sim gives away your whole chip design; while a SPICE
run is just a small sub-circuit at best.
Synopsys wants to be your company gatekeeper SysAdmin by relaunching
its DesignSphere.com cloud computing SaaS from 2000. Now its online
burst VCS or HSPICE is on 100% Synopsys-controlled Amazon EC2 servers.
"Look, Aart!, we locked out Magma!" Ask for David Hsu. (booth 3433)
- from http://www.deepchip.com/gadfly/gad060211.html
From the user comments, it appears that Rajeev has his own Magma Cloud for
SPICE simulations quietly in the works, too.
On the SPICE-add-on tool front, rumor is that Solido picked up a sweet $3 M
in series C funding. Qualcomm, Huawei, and NVIDIA are known users.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
FineSim shows improved speed and accuracy. Found it to be faster than
SNPS, good accuracy. They're adding a Tcl interface to FineSim and
ability to stop a simulation midway to check the output and modify
the input to complete simulation. A huge benefit if it really works.
Another interesting feature is it can take in a SPEF and verilog netlist
input to run a simulation over a digital/analog interface.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I was in the Magam FineSim DAC demo. It has improved quite a bit over
the years. Visually it's much more coherent going back and forth and
handling different formats of input and working with different levels of
hierarchy. But most important part is simulation throughput boost with
large designs. Apparently the parallelism and E2M made the performance
boost possible.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We use Berkeley AFS because of its speed. Thank God neither Aart nor
Lip Bu has bought them yet.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
c) New Mentor engine for large SPICE circuit: Eldo Premier has very
good results from first testing.
- Angelo Contini of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
The Solido Variation Designer tool rolls up the different analyses into
one cockpit to do:
- PVT corners analysis
- Monte Carlo analysis (and high sigma Monte Carlo)
- understands layout dependencies
- relevant data visualization
I like their sampling process for Monte Carlo analysis, reducing the
# of simulations needed to get the right accuracy and yield confidence.
For us, it's critical to achieve a low defect-density levels for yield
of our analog/RF modules. It is just too expensive to throw away an
SoC when a key analog parameter is out of spec.
I also like their High-Sigma Monte Carlo analysis. Typically used in
memory and highly repetitive design structures.
My background is in nanometer A/MS design for wireless processors with
very high volume expectations. To me Solido is the Swiss Army Knife for
variation design giving the custom designer everything needed to explore
the design space and make quantified trade-off decisions.
- Mohamed Kassem of Stone Soup Labs, Inc.
---- ---- ---- ---- ---- ---- ----
We like Solido. For example, our analysis could be set up by specifying
a target yield or by using worst case design corners to identify
trade-offs.
After all of the selections are made, Solido will begin working on the
problem from within the design environment and it takes advantage of
common SPICE simulation management environments such as LSF or SGE.
Once Solido completes its run, the results can be used to recommend
design adjustments and maximize yield, reduce power and minimizearea.
This is enabled by Solido's Design Sense. Design Sense is a set of
contour plots that allow the user to observe the interaction among
analog parameters in real time. This feature was noticed by several
people from my organization as a differentiator.
- Cyndi Recker of Freescale Semiconductor
---- ---- ---- ---- ---- ---- ----
Monte Carlo runs are too long. I like Random Dopant Fluctuation (RDF)
and Line Edge Roughness (LER) functions you find in Solido.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I saw Solido's DAC demo. Solido says Variation Designer is interoperable
with SPICE and FAST SPICE tools; which allows variation analysis to be
done on the chip level, not only block or circuit.
For example, you could analyze the variation impact on:
- Setup and hold times from pin to pin
- Different data paths within a chip (local variation) and
from chip to chip (global variation).
We do analog and custom memory design. Static timing over corners has
been around for long time. Our headache is statistical analysis on top
of static timing. That's where Solido might be able to help assuming
some extra cooperation with the foundries as well.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended a 1 hour demo session of Solido Variation Designer. Solido
was demonstrating 2 new capabilities this year: High-Sigma Monte Carlo
and Fast PVT.
HIGH-SIGMA MONTE CARLO (HSMC) demo highlighted:
1. You can use HSMC to design and verify a circuit up to 6 sigma in
a few hundred simulations instead of what would otherwise take 5 billion
Monte Carlo simulations.
2. All results are SPICE-accurate so you can simulate any failing points
in your simulator.
3. It's scalable to hundreds of variables.
4. HSMC gets the simulation improvement by doing a smart sampling that
figures out how to bias the samples to the tails of the distribution.
5. HSMC can also do design parameter sensitivity analysis on failing
points to show the user how to get the design to the desired sigma target
if it's not already meeting the sigma target.
6. Solido said its High-Sigma Monte Carlo has been qualified in the new
TSMC AMS Reference Flow 2.0.
For the FAST PVT demo, Solido showed:
1. Fast PVT can reduce the number of process, voltage, temperature, load
corner combinations that need to be simulated by up to 50x.
2. They have algorithms that figure out the worst-case corners without
having to simulate all of them or the user having to guess which corners
are worst.
3. As with HSMC, Fast PVT provides design sensitivity capabilities to let
the you know how to make the design work under any failing conditions.
4. Fast PVT has also been qualified in the TSMC AMS Reference Flow 2.0.
Solido said Variation Designer is integrated with all the major SPICE
vendors including Synopsys, Cadence, Magma, Mentor, BDA. They also
showed how they have integrated into Fast SPICE simulators and can
parallelize variation jobs across many simulators at once.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I have not yet tried it out myself, but if Variation Design does what
Solido claims, I think it would be a valuable design tool for any
circuit designer. The tool seems well thought out and easy to use.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
2) Coupling Wave Solutions - They seem to promise quick & accurate noise
analysis through the substrate for large analog/mixed signal SOC's in
a reasonable amount of time. This is important as if you are seeing
noise-coupled-through-the-substrate. It can be very costly to find.
3) Apache - Showcased there new ESD solution PathFinder. This promises
to do layout based full-chip analysis of ESD events in a reasonable
amount of time. A comprehensive, quick ESD solution has been
difficult, so a deeper look at this tool is warranted.
- Chris Geen of Analog Devices, Inc.
---- ---- ---- ---- ---- ---- ----
WaveIntegrity from CWSeda, since it looks promising to handle noise
coupling issue.
Some cloud computing service from Synopsys, good thinking of leveraging
computation power.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
a) Liked the new GUI manage the mixed signal VCS-XA. It's a good
help in order to set and run the simulation.
- Angelo Contini of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
Synopsys Cloud because it allows designers to run huge amount of SPICE
simulations on powerful machines with a very large number of licenses.
It is very useful for peak usage or to run heavy Monte Carlo analyses
with hundred thousands of simulations.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended the Magma SPICE booth at DAC. Got good insight into the focus
areas for Magma from a cloud perspective.
- [ An Anon Engineer ]
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