( DAC 11 Item 10 ) ---------------------------------------------- [10/13/11]
Subject: Calypto CatapultC, Forte Cynthesizer, Mentor Vista, Xilinx
SEA CHANGE: The biggest news in ESL has been that Mentor traded its entire
Catapult C team to Calypto, causing all sorts of public speculation of how
fundamentally "heathly" or "unhealthy" the SystemC-based-design space is.
Mentor rumored to have traded its Catapult C division for Calypto
Kludgy, nichey SystemC/C/C++ synthesis forced MENT to dump CatC
Carl Icahn accountability forced MENT to trade away Catapult C
ChipVision developer agrees C synth is like teaching a dog to dance
User asks now what's the future of Mentor DK Design Suite/Handel-C?
Calypto finally spells out the details behind Catapult C merger
Regardless, the user comments easily have Catapult C still as #1, with
Forte Cynthesizer as still a strong #2 in C-to-RTL synthesis, and
Cadence C-to-Silicon as a weak #3. No mention of Synopsys Synfora nor
Synopsys SystemC CoCentric Compiler anywhere to be found.
Rumor has it Xilinx paid $25 to $30 million for AutoESL. See ESNUG 482 #6.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
I think the Mentor Catapult C presentation was quite interesting. I was
mostly interested in the low power aspect of the tool.
- Amir Gourgy of Research In Motion, Inc.
---- ---- ---- ---- ---- ---- ----
Mentor's Catapult C Synthesis demo looked good.
As the name implies, Catapult synthesizes C code and skips the RTL coding
stage; which would give us a time savings. However, we are not currently
using C as a top level language, we are using VHDL.
This is something for us to look at more closely in the future.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We use Catapult C synthesis as a proof-of-concept to go to gate-level
simulation.
Our design language is VHDL. We would like to also do model-based
engineering to speed up the process, but right now we understand (from
the ESL Symposium) that model-based engineering needs hand modifications
for VHDL.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Catapult
We currently use a Verilog RTL design flow right now but we're trying
to align ourselves with a C-based methodology at DAC.
Catapult C seems handy for more abstract/generic descriptions. Our
designs are growing and we need to assess the whole CatC top down
methodology all the way from generating a design from a spec.
The Catapult folks claim they can handle complex designs and reduce them
to RTL, as a less error prone method than manual RTL creation.
Our current Verilog method is working, but we will consider Catapult as
designs get complex. We expect to take a closer look after we complete
our next couple of design projects.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
a) C-to-Silicon (C2S) from Cadence
This high-level synthesis tool has promising technology such as TLM. The
area/frequency results I have seen in pilot deployment are encouraging
and we are actively looking at broader use considering the productivity
gain and QoR. The methodology connection to virtual prototypes is
important, but I have not seen results yet.
b) SLEC from Calypto
Critical to make TLM the golden source. The connections to high level
synthesis seem to be necessary, but it makes me nervous.
c) Cynthesizer from Forte Design Systems
This high-level synthesis tool has built-in interface and memory IP
generator. That's attractive.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
An interesting DAC backroom discussion gave me the scoop that Forte is
working with Oasys synthesis to produce an integrated SystemC-to-gates
synthesis flow.
Forte already has co-operative flows that allow Forte to produce RTL
output that is then sent to Synopsys DC, Cadence RC, Magma -- but Forte
is partnering with Oasys to get congestion feedback that will then be
used by Forte to improve the Forte-output that is then sent back to
the Oasys tools.
Apparently Forte and Oasys have joint customers that have requested this
partnership, and Forte has heard very good things about Oasys synthesis
results from their joint customers.
- Cliff Cummings of Sunburst Design
---- ---- ---- ---- ---- ---- ----
c) NEC Cyberwork bench - The demo was not impressive as compared to
Mentor/Forte/etc but the Thursday afternoon user track session was
compelling. The ability to plot the QoR for various trial HW
architectures automatically looked interesting.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Mentor Vista
15 years ago we used to use a performance model - e.g. how many clocks it
took; this worked well, but was a dead end for us.
We now have Vista in-house. With it we can do trade-off analysis. We do
a quick design in C, make sure timing is correct. We then use Vista's
timing diagrams as templates for our VHLD design team to use & match to.
We are working closely with Mentor AEs on this. It takes more time and
experience to learn to code designs in C than to use an icon-based
approach, but over time this C design approach has more potential and
flexibility.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
For years I have been a proponent of using C code for modeling designs in
logic verification. At times this can be cumbersome for designers, as
they have to create two versions of their designs in two languages.
As ESL matures it provides a path to build designs at higher abstraction
level and eliminates the need for two designs created for RTL and
modeling. SystemC provides advantages such as early system modeling,
early software validation and model reuse.
Mentor appears to be positioned well for this transition with its Vista C
offering for ESL design.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Vista
ESL and these formal/assertion verification techniques. Part of our
verification techniques. A little more ahead.
We saw Mentor's Vista DAC demo. We don't specifically use Vista now,
but are moving towards doing modeling and verification at a higher level.
We're an old fashioned Verilog house and are moving up in abstraction.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I was at the Mentor Booth.
Of course, more than just Mentor is supporting ESL with Vista, but that's
one of the reasons ESL has reached this maturity.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
No.1 Socrates @ Duolog
Because I'm interested in a simple model creation and IP-XACT.
No.2 VisualSim @ Mirabilis
Because I'm interested in a power consumption on ESL.
No.3 DDGen @ Vayavya Lsbs
Because I'm interested in simple fast program creation in ESL.
- Arakage Masaharu of Nikon Corp.
---- ---- ---- ---- ---- ---- ----
2. TSMC supporting ESL in their Reference Flow 11. I got a chance to
talk with the TSMC guy, and he really knew his stuff. I asked him why
TSMC would have any interest in ESL (about as far from silicon as you
can get and still be in EDA), and he essentially said that you have to
give users tools to do something with 1 billion transistors.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
1. Xilinx's support of high-level synthesis to enable more low-volume
designs on FPGAs
- [ An Anon Engineer ]
Join
Index
Next->Item
|
|
