( DAC 11 Item 4 ) ----------------------------------------------- [09/28/11]

Subject: Magma CHILL, Docea Aceplorer, Cyclos Cyclify as #4 hot tool at DAC

LESS IS MORE: For quickie netlist power reduction, Magma CHILL got the most
user interest.  On the ESL level Docea Aceplorer got some user interest,
while Docea's SystemC rival, ChipVision, went out of business this year.

Cyclos Semi and a weird little shop that goes by the name "Just Chillin"
are two stealth power start-ups that got noticed, too.

    NEW TOOL - Magma CHILL does netlist-based dynamic power reduction
    through combinatorial and sequential clock gating.  Since it's a
    netlist tool, you can use it in a SNPS/CDNS/LAVA/MENT/ATOP flow
    with no special tweaking needed.  It's an easy out-of-the-box 20%
    to 30% power reduction.  (booth 1743)  Ask for Mark Richards.

        - from http://www.deepchip.com/gadfly/gad060211.html

     "What were the 3 or 4 most INTERESTING specific tools that
      you saw at DAC this year?  WHY where they interesting to you?"

         ----    ----    ----    ----    ----    ----   ----

   The Magma CHILL demo was very interesting.  I liked that all the power
   optimization steps can be done with a gate-level netlist.  Would be
   interested to know more about logic equivalence checks for sequential
   enabled insertion.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   I had an opportunity to learn about Magma CHILL at DAC.  From the
   description, it is a good addition to a tool kit for reducing dynamic
   power.  The tool automatically inserts combinational and sequential
   clock gates in a gate-level netlist.  Their claim is dynamic power
   reduction of mid to high single digit percentage for a netlist that is
   already well clock gated.  The tool has formal checks to alleviate
   concerns about equivalence failures due to addition of sequential clock
   gates.  With netlist in and netlist out, the tool can be used as a
   standalone with any flow.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Our designs typically mean integrate bunch of legacy IPs, mix of Verilog
   and VHDL RTL.  (Power savings and making schedules are our top 2 goals.)

   I was particularly in hunt for a power reduction tool which did something
   more than clock gating at netlist level.  I felt Magma CHILL was right on
   spot.  We have yet to look into evaluations, but demo was impressive.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Magma CHILL -- 20% to 30% power reduction with no tweaks?  Other than a
   price negotiation, what's not to like?

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Why would LAVA sell CHILL?  Use it two or three times on your gate-level
   netlist and it's done all the power reduction it can do.  No one wants a
   tool like that.  They should rent it out instead.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   DOCEA ACEPower: estimation and visualization of complex power consumption
   model, floorplan-aware thermal estimation.  We plan to evaluate it.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   I was particularly interested in the Docea Power Aceplorer tool to model,
   estimate and optimize power consumption at the system-level.  I have been
   very interested in finding such an ESL tool for a while because I'm the
   system-level power lead for a number of mobile projects at my company.
   However, I had not come across such a tool before.

   With Aceplorer, I can model power of the entire system at a high-level
   and run power simulations to generate dynamic current profiles for
   different use-cases.  The tool also allows cross-functional teams to
   collaborate on power using a common framework.

   We're currently in the process of evaluating this tool in further detail.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   I liked Teklatech's approach to power management.

       - Tom Minot

         ----    ----    ----    ----    ----    ----   ----

   CYCLOS Cyclify:

   In my opinion, the 3 most difficult design challenges we face today are:
                (1) Timing closure at high frequencies,
        (2) Power optimization as the whole world is trying to unplug,
              (3) Verification complexity and run times.

   Cyclos is the most promising technology out there to address the first
   two challenges.   Cyclify does high performance clock-mesh design by
   building custom inductor circuits to recycle power in your design.

   Cyclos can take a clock tree design that has lots of guard band, very
   deep insertion delay, and that can't meet its target frequency or power
   goals -- and solve these problems by inserting a custom built tank
   circuit and clock-mesh that recycles the power.    The mesh nearly zeros
   out the clock skew and greatly reduces the insertion delay (and thus
   reduces buffers/inverters).

   Cyclify technology can deliver predictable, sharp clock edges uniformly
   throughout your SoC without the big uncertainty settings.  Reducing the
   guard bands has the effect of expanding the timing window available to
   meet timing; thus making the chip run faster.

   Cyclos shared real silicon results with me based on an ARM9 and I was
   blown away.  After hearing the Cyclos pitch, I thought of what the Toyota
   Prius did for cars when they removed the brakes and put in regenerative
   braking.  It's the same idea behind storing the clock current, instead of
   trying to bleed down an RC network, just to re-charge it a split-second
   later...  Cyclos is the only EDA company, IMHO, that can claim they are
   working on a truly "green" solution - 30% power savings is going to make
   a huge impact on some of our future mobile devices...   I wouldn't be
   surprised to see a 3+ GHz ARM core in the future with Cyclify tank
   recycle circuits as the enabling technology.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   b) Just Chillin.  New startup showing a signoff power measurement
      and/or verification tool called "DownTime" and a power optimization
      engine called "Igloo".  The CTO has been working on DownTime for
      about a year now.  Igloo is an optimization tool he wrote while
      working on DownTime, and claims 20% dynamic power savings and up
      to 30% leakage saving.  Reports from both tools could be viewed on
      your iPad, which was pretty cool.  (He even showed in his demo how
      you could swap between Farmville and Igloo which got a good laugh.)

          - [ An Anon Engineer ]
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