( DAC 11 Item 3 ) ----------------------------------------------- [09/28/11]
Subject: Users rate Oasys RealTime as the #3 "hot" tool at DAC'11
YEAR 3: This is the third year in a row where Oasys RealTime has made my DAC
Users Top 5 list. Taking on the Microsoft of EDA (especially on their home
turf of RTL synthesis) won't mean victory in a day, but it looks like Oasys
is getting steady traction with those bleeding edge users who must squeeze
out every Mhz and mm2 they can get. And that Forte deal looks good, too.
Oasys RealTime takes your chip's RTL and floorplan to placed-gates
"10X to 60X faster than Synopsys DC-Graphical can." Verilog, VHDL,
System Verilog, multi-mode synthesis, DFT, UPF/CPF low power design.
Their DAC demo is a *live* 30 min run of 300 K lines Verilog, 1.6 M
instances, 45 nm lib, 1.2 Ghz, full chip physical, low-power, DFT.
Texas Instruments, Juniper Networks, Netlogic, Xilinx uses them.
- from http://www.deepchip.com/gadfly/gad060211.html
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
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We looked at Oasys this year and we think they have matured a lot this
year. The tool has crossed the hype cycle and now showing traction.
We were quite impressed with the numbers that they showed us in their
presentation (still marketing #s and may not be 100% credible). Their
technology and the explanation behind the benchmarks seems to justify
their numbers.
One thing which is still not there Oasys support for retiming. We will
be evaluating the tool soon to see if what they claim is all true in
our designs. I will send you another update after our evaluation is
complete.
- [ An Anon Engineer ]
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I saw the demo of Oasys' RealTime. It looks impressive. I recommended
we do an eval to my management.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Synopsys Star-RC updates and Oasys RealTime.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
It's time for us to give Oasys another look.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Tuscany, Oasys and Tekton
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Oasys -- 10x+ physical synthesis speedup? Who wouldn't be interested?
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Oasys. We're always looking for viable Synopsys alternatives.
- [ An Anon Engineer ]
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OASYS:
I have attended Oasys DAC demo for 3 years. If I could build my dream
flow, I would replace my Cadence and Synopsys flows by putting together
Oasys, Atoptech, Extreme, Apache and Cyclos. Oasys clearly has the tool
for next generation, very large scale synthesis. I push the purple
button every day and I don't see Design Compiler anywhere close to
RealTime. RealTime Designer has grabbed some traction over the last
year and several new customers were added to their portfolio (I remember
TI and Qualcomm). I also saw a lot of new faces at the Oasys booth,
among them some ex-SNPS A/Es... I gather the company is doing well and
continues to expand and hire as the product matures.
Technically speaking, Oasys showed off new power features, DFT features,
and better compatibility with the Big Four backend flows... and, of
course, it had many examples of very large, very fast synthesis. At my
job, I run 1.5 m instance blocks thru the purple solution and it takes
forever -- seems like Oasys can do it over a lunch hour. Some of the
highlights - CPF/UPF fully supported, level shifter insertion a breeze,
1.6M instances reads into tool in 2 minutes, Leakage and Dynamic power
optimization automated, scan stitching and reordering supported, System
Verilog supported, enhanced SDC support (filter_colleciton, get_cells,
group_path, all_fanout, etc).. and one big one - it reads in cap tables
and writes out DEF.
Oasys claimed that 50% of the top semi companies are evaluating Oasys
right now. It reminds me a lot of when Cadence bought Get2Chip. I
would not be surprised if most of the bleeding edge and big designs will
be using Oasys in 18 months. I am watching for some big logos to come
in 2011. At DAC this year, I saw a lot of "me-too" timing, power, SI
solutions, but I didn't see anything that compares with what Oasys has
produced. Because Realtime is still un-challenged after 3 years, I
would continue to rate Oasys RealTime as one of the most compelling
tools out there and a "must-see" for anyone doing digital design.
- [ An Anon Engineer ]
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An interesting DAC backroom discussion gave me the scoop that Forte is
working with Oasys synthesis to produce an integrated SystemC-to-gates
synthesis flow.
Forte already has co-operative flows that allow Forte to produce RTL
output that is then sent to Synopsys DC, Cadence RC, Magma -- but Forte
is partnering with Oasys to get congestion feedback that will then be
used by Forte to improve the Forte-output that is then sent back to
the Oasys tools.
Apparently Forte and Oasys have joint customers that have requested this
partnership, and Forte has heard very good things about Oasys synthesis
results from their joint customers.
I also found it interesting that Forte produces synthesis scripts that
can be used to drive the RTL synthesis tools of each of their partners.
This gives Forte customers a very interesting way to benchmark
competitive RTL synthesis tools to find out which tools give the best
overall results for their Forte designs. It will be interesting to see
if Oasys tools pick up a significant advantage from the congestion-info
feedback partnership.
Now if I could talk the Forte folks into pursuing a "Synopsys" SV model;
define a SystemVerilog HLS (High Level Synthesis) subset that they would
automatically translate into compatible HLS SystemC, for those of us who
do not care to code anything in SystemC. (Brett - hint! hint!). If
Brett were to show me that tool at DAC next year I would really sing
praises to Forte in my DAC report next year!
- Cliff Cummings of Sunburst Design
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