( DAC 11 Item 2 ) ----------------------------------------------- [09/28/11]
Subject: Vennsa OnPoint, NextOp, RealIntent Ascent XV as #2 hot tool at DAC
THE UNUSUAL SUSPECTS: Vennsa OnPoint plays the blame game by seeking out and
telling you who's probably causing the exact bugs you're experiencing. They
call them "suspects". The neat thing is it's AUTOMATED; the only time a
human is needed is to check the final "suspects" out.
Rumor has it that Craig Shirley, the VP of Sales at Apache, has now signed
on to be NextOp's new VP of Sales. If true, that's impressive.
Vennsa OnPoint does automatic root cause analysis of failures. It
shows "suspects" pointing to the actual bugs with no user direction
needed. Simular to Springsoft Verdi. See ESNUG 492 #4. Panasonic
uses it. (booth 2912) Ask for Sean Safarpour. Freebie: key chains
- from http://www.deepchip.com/gadfly/gad060211.html
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
I like Vennsa's debug tool OnPoint because debug is such a painful manual
process and this is by far true-automation for debug. It's something
that is much needed yet it does not exist outside of Vennsa.
- Jayanta Bhadra of Freescale Semiconductors
---- ---- ---- ---- ---- ---- ----
I looked pretty closely at the Vennsa OnPoint tool. I believe they have
some useful technology that is well suited to debugging Formal Proofs,
but Vennsa is insisting they can make it work in the simulation space.
I am skeptical that Vennsa can focus on both the formal and simulation
space and be successful. Simulation debug automation is a very tough nut
to crack and will take more than just a single technology breakthrough.
Also, I am not clear on the incremental value of the technology over the
robust debug features offered in a formal tool like Jasper Gold. Vennsa
has new technology, I just cannot tell what it is worth. It will be too
expensive if they are not focused.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Vennsa Onpoint -- it looks like it can help us take our DV productivity
to the next level.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
At DAC I saw three companies, Vennsa OnPoint, NextOp Software and Avery
Design that are on the right track, and most likely to enable significant
breakthroughs.
I believe the next verification break through will come from combining
several techniques (simulation, static analysis, and formal methods) with
several data sources (simulation wave data, regression results and
knowledge of source code changes) to optimize the overall problem of
incremental regression testing.
- Dylan Dobbyn of Teradyne
---- ---- ---- ---- ---- ---- ----
One of the new tools that I found interesting at DAC this year is OnPoint
from Vennsa. It is a debug tools that has the potential of significantly
improving the turnaround time for RTL debug.
- Nihar Mohapatra of Huawei Technologies (USA)
---- ---- ---- ---- ---- ---- ----
2. Vennsa "OnPoint"
With all the talk at the Vennsa booth on diagnosis and triage, I
became interested because I wondering who was ill. Apparently, it's
my RTL! It seems that Vennsa' "OnPoint RTL Doctor" finds suspects
(not just the usual ones) in the RTL code that is causing a
particular bug in your design.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
2) Vennesa automated debugger - The automated debugging help would be a
next step. Even though not sure how much they scale to for bigger
circuits and the time it takes to bring the ranked potential error
places. It can make the life of the verification/design engineer lot
easier. Lots of innovation is actually required in this area and
Vennsa is the first one in it.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
NextOp because it completes verification test plan showing designers
which are the weak points in their verification phase so that they can
fix them improving the coverage.
- Pierluigi Daglio of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
We use NextOp BugScope's automatically generated properties as part
of our functional verification for design and integration of IPs.
- The coverage properties identify functional coverage holes.
- The assertions help us detect and fix bugs early; even before
checkers are complete. BugScope's assertions also reduce the
time to verify proper IP integration because they capture
the IP usage requirements.
- Generates properties that enable designers early insight that
may lead to modifications that improve their design approach.
We are able to utilize approximately 90% of BugScope's generated
properties in our simulation flows.
- Alan Coady of IDT
---- ---- ---- ---- ---- ---- ----
1. NextOps Assertion Synthesis Tool "BugScope"
I find this tool interesting not only because it automates the task
of creating white-box assertions through generating easy-to-read
properties, but also because BugScope has the power to mask out
assertions that duplicate the RTL code.
The properties generated by BugScope provide unique corner case
assertions not anticipated by designers. In addition, bugs can be
found just by examining the properties, thus saving on simulation
and overall debug time.
NextOp also unveiled a new GUI interface for BugScope to enhance
user experience at DAC this year.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
NextOp BugScope helped our design team get started w/ formal verification
methodology. The tool is quite easy to use. Its automatic generated
assertions are quite useful.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I saw a demo for NextOp's BugScope assertion synthesis tool at DAC.
BugScope takes an existing regression suite and test bench, and
automatically generates insightful assertions for you.
The way I understand it, the designers review the properties generated by
BugScope. If the property is true universally, then it's an assertion.
If not, then the property points to a coverage hole. Even if you then
fill the coverage hole, you still need the assertions as coverage aids.
Traditionally, we have relied on an OVL library, and converted them to
System Verilog Assertions. We've been DV resource constrained, so it
would be attractive to have our DV team create a minimal testbench and
some sanity tests for our designers to use as inputs to BugScope. Our
designers could then qualify the assertion and coverage properties
generated, and hand the test environment back to our DV team with the
checking and coverage assertions annotated.
This would offload some of the DV team's work, and lower the barrier to
broader adoption of an assertion-based verification methodology.
- Joseph Hanli Zhang of Cisco Systems
---- ---- ---- ---- ---- ---- ----
I talked with the folks of NextOp and concluded BugScope's main value
will come when the assertions are inserted into code based on testbench
and test code that will also test that code. They seem to do some of
that, but I haven't studied it much more than that.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
NextOp's BugScope seems interesting and worth looking into. We will
bring them in to give an overview to the team.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
As for the NextOp's BugScope product demo, I certainly liked their idea.
Their assertion synthesis is somewhat a new approach to generate
assertions automatically. Although it is automatic generation it
requires some aids from the designers, that is a very limited number
of simulations to toggle as many topological interfaces as possible
as part of the exploration step.
After that the tool is able to generate assertions at the block-level as
well as at the chip level.
The GUI was good, as I recall. The main attraction of this tool is that
it makes the design verification process easy and increases the overall
productivity of the design resources. The quality of the assertions
generated seems to be very decent.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
1) Jasper Active Design/Properties: I particularly like the running
proofs on spreadsheets.
3) Cadence's automatic proofs of line coverage results and updating
the coverage report. This is great fit for their formal technology!
I would like to see integration with other tools.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
They showed me Ascent XV X verification part which I am interested. It's
a useful tool, covers static X verification and dynamic X verification.
I think that the drawback is that the main X source is DFF without reset,
but the Real Intent tool does not cover how to verify whether DFF is X
after initialization.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Editor's Note: If you have first-hand experience doing X verification with
Real Intent's Ascent XV, (or evaling it) please drop me a line. - John
Join
Index
Next->Item
|
|
