( DAC 11 Item 1 ) ----------------------------------------------- [09/28/11]
Subject: Users rate Mentor Olympus-SoC as the #1 "hot" tool at DAC'11
ELEVEN BIG NAMES: Get 11 big name customers to endorse a Verilog simulator
is no big thing -- because there are over 3,000 companies using Verilog
simulators. Getting 11 big name customers to endorse (albeit most of them
anonymously) your nascent digital P&R tool *is* impressive, because there's
less than 200 significant total possible digital P&R user co's available
worldwide. Nvidia, ST, AMD, and Fujitsu are already publically known users;
*I* was impressed when 7 other Big Name users emailed me endorsing it. (Not
too bad for a tool that was #1 on my Cheesy Must See List For DAC 2005.)
Mentor Olympus-SoC has "new features for TSMC & GlobalFoundries 28 nm
processes." Hierarchical stuff, macro analysis and placement, rapid
prototyping, advanced block shaping, clock planning and chip-level
assembly, proprietary modeling, flow parallelization and MCMM stuff.
- from http://www.deepchip.com/gadfly/gad060211.html
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
B) Mentor Olympus:
We're an early user of Olympus (back when it was Sierra Pinnacle). It
was used as a point tool to supplement of our existing Synopsys PD flow.
I was impressed after seeing the demo and the customer presentations.
It seems that more and more customers have used Olympus as their main
physical design suite. In the presentation, ST Ericsson had given a
lot of detail about their experience using Olympus of variety of mobile,
baseband and modem chips. They talked about complete place and route
methodology for a GHz modem using Mentor Olympus. They also talked
about fast prototyping and floorplanning work with Mentor. Also in
Olympus suites Mentor was talking about interesting features in rapid
prototyping, automatic macro analysis, macro placement, clock tuning
and clock planning.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
STmicro specifically talked about how they used Olympus to do PnR of
mobile and digital baseband chips with 20+ multi-mode, multi-corner
scenarios. It looks like they are actively using Olympus in their flow
and are able to do large multi-voltage designs with lots of scenarios.
There seems to be a good partnership between ST Ericsson and Mentor on
tool development and methodology.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I found the Olympus Place & Route suite session very interesting.
They demonstrated a complete hierarchical flow including prototype
placement, macro placement and clock planning. The ability to identify
congestion due to clocks early on in the design flow is very useful.
Their top level clock tuning methodology was also pretty neat.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Olympus-SoC hierarchical prototyping capabilities seem impressive. They
seem to have promising technology for both macro placement and also macro
analysis in terms of reducing the number of iterations required. If it
works, that could seriously reduce our PnR TAT. (We'll see.) Their
turbo prototype placer also seems to be quite fast for early feasibility
analysis.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
MENT Olympus Place & Route suite sessions included customer experiences
using the tool. GlobalFoundries presented on Olympus DFM capabilities
including recommended rules flow was impressive. GF and MENT have
correlated their DFM scoring methodology to ensure consistency in the
yield scoring. The tool appeared to let you have flexible priorities
for the various recommended rules. Sawicki runs an impressive R&D.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
At DAC this year, several customers of Olympus place & route tool were
presenting their user experience at Mentor's booth. One customer, Kalray,
a start-up in France, presented a network-on-chip 28 nm design. Their
design had 256 processor cores with multiple voltage domains. It was
completed using Olympus place and route. They claim the reason they
used Olympus was because of its ability to handle large capacity,
multi-threaded routing and timing analysis, multi-corner multi-mode
based multi-voltage flow, and built-in Calibre signoff inside Olympus.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended the Olympus P&R session this year at DAC. Their hierarchical
design flow demo seemed fast. I like their idea of turbo prototype
placement, automatic macro placement and clock planning and clock tuning.
The run times for each stage of the flow was impressive, especially in
the macro placement stage.
- [ An Anon Engineer ]
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