( DAC 10 Item 11 ) --------------------------------------------- [ 11/19/10 ]
Subject: Mentor Olympus, Atoptech Aprisa, Magma Talus
AND THREE BECAME FIVE: The most recent customer license-use data available
for the digital P&R market comes in two parts. First the floorplanner use:
2007 - Cadence First Encounter: #################### 49%
Synopsys Jupiter-XT: ############ 30%
Magma Blast Plan Pro: ####### 18%
Internal tool: #### 10%
and then the actual placer-and-router license-use:
2007 - using Synopsys P&R tools: ############################ 56%
using Cadence P&R tools: ################ 31%
using Magma P&R tools: ############# 25%
Since 2007, Magma "won" the lawsuit vs. Synopsys, Mike Fister and his Gang
of Four finally "resigned" from a crippled Cadence, Mentor Sierra and
Atoptech both "arrived", and the world economy crashed.
Only God (and perhaps Gary Smith) knows what the current equivalent 2010
license-use data looks like.
Anyway, from the comments I've received, it appears that the DAC'10 users
didn't look much at the SNPS & CDNS digital P&R tools (maybe cause of those
weekly visits from 2,000 Synopsys and Cadence reps) but instead they spent
their precious DAC time to shop the Magma, Mentor, and Atoptech tools.
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
Mentor's P&R system is two products. Pinnacle is a "physical synthesis"
tool that does floorplanning, placement, optimization, clock tree
synthesis, and global routing. Their Olympus SOC tool does detailed
routing, then Pinnacle cleans things up post route. The MENT salesman
said they sometimes sell Pinnacle separately but Olympus is basically
always sold with Pinnacle.
- John Weiland of Abraxas Corp.
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I attended the Mentor Olympus P&R session at DAC this year and found it
to be very interesting.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Olympus-Soc: P&R for 28 nm. Mainly for partition implementation with
MMMC and a full-flat chip assembly flow. It has concurrent optimization
for multiple process corner and design modes. It can optimize large
chips full flat while keeping logical hierarchy and physical boundaries.
Calibre InRoute is interesting as it solves DRCs upfront while doing
backend implementation.
- Pooja Arora of STmicroelectronics
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I think Mentor Olympus is good.
- Jun Li of Trident Microsystems, Inc.
---- ---- ---- ---- ---- ---- ----
I reviewed the Mentor Olympus P&R session at DAC this year. They
expanded Calibre InRoute to handle recommended rules, pattern matching,
antenna fixing etc. Their new macro placement was interesting. I
think they are headed in the right direction.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Synopsys DC-Graphical, IC Compiler and the Olympus design suite looked
interesting for me.
- Arvind Kumar of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
The Olympus place and route suite was very interesting. Their "Genesis"
macro placement engine and physical verification signoff with Calibre
InRoute were both very promising.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Atoptech sells a tool that does floorplanning, place and route, clock
tree synthesis, and chip assembly. They say it was written multi-
threaded from the start and can do concurrent multi-corner multi-mode
place and route 3X to 10X faster than competitors. They say it does
very accurate global routing and fixes SI problems before going to
detailed route, which saves time. They say it is easier to use and
debug than competing tools as well.
- John Weiland of Abraxas Corp.
---- ---- ---- ---- ---- ---- ----
I also attended Atoptech's demo and I certainly found it impressive.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
AtopTech:
This is a 4 year old company. This is a pure place and route tool which
is responsible for floorplanning, placement, clock tree synthesis, metal
routing, SI issues and finally post-DFM handling issues. It can do
multi-million gates with standard logic, memory blocks and IP's. This
can be done flat or hierarchically. Can simultaneously operate at MCMM.
I still have not used this tool, but would like to use it someday.
What I hear is Atoptech's hierarchical, floorplanning with physical and
timing budgeting is their strong point and handling pin issues at various
levels of floorplanning is superb. From the demo that I attended, Atop
had all the features of regular place and route tools. However, I do not
know about its low-power implementation features, since its customers
were dealing more with 65 nm than 45 nm. Their R&D is strong.
- Ashok Chinnagiri of MaxLinear
---- ---- ---- ---- ---- ---- ----
From the Broadcom DAC presentation I got the impression that Atoptech is
in the same situation as Magma was in 2001: trying to be a disruptive
technology -- not necessarily the best P&R solution out there, but very
user-friendly and fast so that they can start replacing an incumbant on
small, low-complexity designs quickly, then work their way up.
But there are 2 key differences between Magma then and Atoptech now:
1) people now don't really care about what tool they use for
low-complexity designs; and there are more choices now, unlike
having to struggle with #$%@&*! Silicon Ensemble 10 years back.
2) Magma did have some unique technology that made them look like
a next generation tool: TCL interface, atomic commands for
optimization that made the user feel like he was in control of
what was going on, supercells, and so on.
Bottomline, I think Atoptech has a 'good' P&R tool, but I don't see a
killer app in it. I'm right now at a point of choosing between three
P&R tools for designs in the next technology node, and I frequently
ask myself if we should consider Atoptech also. But I don't have a
compelling reason...
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Magma showed the status of their new P&R methodology cockpit at DAC.
It is similar to Talus-ACC which Magma developed at one time, no
restriction for floorplanning. Their combination of multi-threading
and distributed processing is a good concept for total TAT reduction
for big designs. I hope this can be achieved 1/n TAT reduction (n is
the number of threads), but the current tool doesn't meet my
expectation... They need more tuning to get better performance.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Magma CHILL
Magma presented a convincing case of Low Power Methodology using their
Talus and CHILL tool. This flow allows optimization of logic blocks
partitioned as power domains. It also integrates dynamic voltage and
frequency adaptation for better power results. Magma claims a 20%
power reduction.
- Rakesh Sethi of Toshiba
---- ---- ---- ---- ---- ---- ----
The folks at Magma emphasized that their Talus Power Pro tools work to
minimize power throughout the flow. They say that RTL power estimates
are too inaccurate and Apache tools come so late in the flow that major
changes can be required. Magma can add power switches and retention
flops using special directive in the RTL (labels in the Verilog blocks
or VHDL processes), add clock gating, multi-Vt design, power grid
synthesis, decap insertion, and power aware buffering. They say they
can mix CPF and UPF for different blocks.
- John Weiland of Abraxas Corp.
---- ---- ---- ---- ---- ---- ----
I attended Magma's DAC presentations on low power implementation driven
by CPF/UPF power formats.
I don't think Magma fully supports CPF 1.1 and UPF 2.0 (supports all the
CPF/UPF commands or the CPF macro-models) but based on customer input
they can add support for CPF macro-models or a more complete set of CPF
and UPF commands.
I believe Magma is the only EDA company which does both UPF and CPF
for low power PnR.
One thing to mention regarding all the Magma presentations: They have
the tendency to oversell/market features which are not fully supported
and optimized in the tools they are providing, with the idea that they
will support/implement them later if the customer wants them. But
they present them as features ready for production today. Sometimes
this strategy can backfire regarding the company credibility. You
really don't know exactly what is really working vs. what is wishful
thinking (in development) when you view Magma's presentations.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
As a newcomber to EDA, the Magma demos were interesting & enlightening.
- Karolina Sarnowska of the University of Virginia
---- ---- ---- ---- ---- ---- ----
Jspeed Design Automation has a router that they say can take placed or
partially routed designs and fix errors made by other routers. They
claim it can handle huge flat designs, reduces wire and via count, and
is much faster than other routers. They now have a European customer
and will engage with others after that project.
- John Weiland of Abraxas Corp.
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