( DAC 10 Item 5 ) ---------------------------------------------- [ 09/02/10 ]
Subject: Mentor Catapult C and Vista
UNHAPPY BRETT: Every time I publish these numbers, Brett Cline from Forte
yells at me that the Mentor Catapult C guys use a different accounting
system which skews the market share in CatC's favor. Gary Smith's numbers:
2008 ESL Synthesis Market: $29.5 million total
Mentor Catapult C ############################## $15.0 (51%)
Forte Cynthesizer ############ $5.9 (20%)
BlueSpec ######### $4.4 (15%)
Synfora PICO ######## $4.1 (14%)
I told Gary Smith. "Although there are differences in the way Mentor does
accounting, they've used it so long that it shouldn't cause any differences
in market share," counters Gary. "Over time these accounting differences
have to converge, just like how Cadence's numbers now converge. Accounting
tweaks only work short term."
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
Catapult C. Sat in on two sessions conducted by Thomas Bollaert of
Mentor Graphics involving Catapult C. Previously, I have used
Celoxica for a client's work and was less than impressed when using
it for real work and not just a demo.
What I have seen so far of Catapult looks good. I am eager to actually
try it in the future. It appears to be more flexible than Celoxica with
working with some of the modules done in RTL. I like the idea of being
able to express algorithms at a higher level and having greater
productivity.
Mentor has a book specific to guiding Catapult to get the results you
want called "High-Level Synthesis - Blue Book". Mentor gave out one
of these at each session, and I won one during the second session. So
all I need now is the tool itself.
- Bob Painter of TurnKey Logic
---- ---- ---- ---- ---- ---- ----
We had evaluated Mentor's Catapult C Synthesis in the past. I took
another look at it at DAC and liked these improvements they made.
1. When we evaluated it, we had some concerns with needing to
learn the coding style that was efficient for high level
synthesis. Mentor seems to have addressed this issue with
their new Bluebook, which reports to take a stab at informing
users of the proper HLS coding style.
2. Mentor added support for SystemC (in addition to C++), for
better support of
- control structures/logic.
- buses and bus interfaces.
Please note that my input on their improvements is only based on
their DAC presentation versus direct experience.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Catapult C seems to be the first (that I've looked at) serious attempt
to bring in high level synthesis into the design flow. I was impressed
with how they have solved the bridge between C-code and hardware by
introducing an interface for defining the physical constraints, e.g.
targeted technology, clock speed, architecture, etc.
It does some sort of pseudo synthesis to quickly find out if the timing
is sufficient to complete a specific operation in X number of clock
cycles and creates pipelining when necessary. Once the you are pleased
with the result, the tool generates RTL ready for Design Compiler.
Now who will be responsible for meeting the physical constraints? Will
it be the design team or the synthesis/implementation team?
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Mentor's talk covered how Catapult-C allows reuse of system development
C/C++ programs to implement the system, including use of SystemC libs,
etc. There was no live demo of a detailed example.
They did introduce Mentor's algorithmic library, with its fixed-point
interface, and a new "blue book" on the language, which teaches good
coding style by examples.
- Jeff Sondeen of USC Information Sciences Institute
---- ---- ---- ---- ---- ---- ----
There are quite a lot of options to choose from in Catapult C in order
to get the result you want (or at least something similar to it) and
the flow is very easy and quick to learn.
However I still have some concerns that CatapultC needs to address.
First of all, I would like to see support in the input description for
SystemC data types such as sc_bv and sc_lv, especially when you already
know the exact bit size of a port and you want to provide it to CatC.
Then I'd like to have far more readable and more understandable output
code, without resorting to labels and gotos.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
After seeing a quick demonstration of the tool Catapult C at the DAC'10,
it seems that High-Level Synthesis is now finally viable. It can even
do low power opto in your design. The blue book they were giving away
seems to be useful, too.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Regarding the Mentor Catapult C demo: To me it seems like all the
C-synthesis products have reached a level of maturity where they can
actually be useful. How Mentor Catapult C stands against their
competitors is of course impossible to tell from the couple of short
presentations I attended.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We are looking for HLS tools mostly for FPGA flows. I attended a Mentor
CatapultC demo in their suite. Notwithstanding the personable and
affable presenter, it was very disappointing commercial-speak.
At the end of a generic slide show, I asked where Mentor considered that
CatapultC had advantages over competitors. The presenter didn't
understand the question!? Just to help him, I asked him why we should
buy CatapultC and not AutoESL and the gist of the answer was that CatC
had been around for longer. So their next release will be ported to
the better OS COBOL then? Overall, unsatisfactory.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I enjoyed Mentor's presentations of Catapult C and Vista, and I had a
telephone technical meeting about Vista afterward because I got a good
feeling from their presentations.
Vista supports modeling, simulation, debugging and analysis based on
SystemC and TLM 2.0.
Catapult is able to convert from SystemC to RTL code which is necessary
to build hardware.
- Shinhaeng Lee of Olympus-CTA, Inc.
---- ---- ---- ---- ---- ---- ----
Mentor Vista 6/14/10
Vista is a design exploration and virtual prototyping EDA tool.
Mentor's presenter claimed Vista can generate a high-level model with
TLM2.0 interface & timing information.
Vista seems to be able to provide the optimization of multi-cores
structure/clock scaling with limited power consumption. For example:
1 core => if clock frequency increased by 20%., then the
performance only improves 13% (but power increases 73%)
2 cores => if clock frequency increased by 20%, then the
performance is improved by ~70%
Vista supports power optimization
TSMC V11.0 reference flow includes:
Mentor Catapult C for High level synthesis,
Mentor Vista special for ESL design exploration,
Mentor Questa OVM for ESL verification
Vista supports debug features by Mentor utility, which is important
to multi-core designs.
- Jen-Chieh Yeh of Industrial Technology Research Institute (ITRI)
---- ---- ---- ---- ---- ---- ----
Mentor sells a variety of products for high level C based design. Their
Visual Elite tool allows the user to define a design graphically and
textually with a mix of System C, VHDL and Verilog. Vista Debug is an
environment that they say understands hardware (versus ordinary C/C++
debuggers). New for this year in Vista is low power smarts. System
Architect allows modeling and analysis of cycle accurate TLM models for
performance and power. Vista Architect uses TLM 2.0 models to allow
architectural exploration. Vista Model Builder creates the models.
Mentor's Catapult C tool goes from untimed C++ to RTL and is the market
leader in this area. It accepts timing constraints from the user and
inserts registers automatically, but allows the user to control the
architecture. TSMC provides libs, but the user can create an IP lib
by synthesizing standard blocks using the user's RTL tools and lib, so
area/speed/power numbers are real. Mentor says they can estimate power
without vectors because they understand the sequence of events that will
occur ("for" loops, etc.), and can do basic MUXed-flop-to-gated-clock
translations, but does not understand different power domains. They
also create a signal in the RTL to show when a block is idle, to
facilitate power shut-off.
They do C++ linting and code coverage and can automatically run your
RTL output with a C++ testbench. They say typical RTL code coverage
is about 70% with C++ vectors. Mentor has written a book of C++ coding
guidelines for Catapult called The Blue Book.
- John Weiland of Abraxas Corp.
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