( DAC 09 Item 13 ) ---------------------------------------------- [12/11/09]
Subject: Biggest lies told at DAC
NEW ENTRANT: I'm used to complaints about EDA marketing claims, EDA tool
incapabilities, EDA prices, EDA support complaints, etc. -- but this is the
first year I got complaints about a fab, TSMC!????
(optional) -- What were the WORST tool[s] or the biggest LIE[s]
you heard at DAC? You can be anon here, but please be specific.
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It's unsettling to see how far TSMC has ventured into EDA, with their Open
Innovation (invasion?) Platform. While technology demands are certainly
increasing the EDA solution complexity at each node, one would hope to see
more collaborative innovation by TSMC with EDA companies, and less efforts
at capturing increasingly bigger pieces of the EDA pie and commoditizing
the rest. This doesn't bode well for the future of EDA market innovation.
Also, there was a noticeable lack of energy in the TSMC booth compared to
past years.
- [ An Anon Engineer ]
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Don't like TSMC OIP. They're choosing who wins and who loses in EDA & IP.
- [ An Anon Engineer ]
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Biggest Lies:
All press releases about 28 nm reference flow for TSMC 28 nm are lies.
The rumored reports from early 40 nm silicon is that TSMC cannot deliver
yielding parts. It's amazing that TSMC orchestrates all the EDA vendors
to make all these claims of advanced flows and none of it has been
tested or works. Call this the "Emperor has no Clothes".
A related lie is the claim of "open" layout verification formats, iDRC
and iLVS. The standard is not published anywhere, not visible on TSMC
website and is not part of any standards body. Open is not open when
controlled by any proprietary organization.
- [ An Anon Engineer ]
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Biggest lie? Sequence. Only way to verify (perhaps) sequential changes
is to buy competitors tool (SLEC From Calypto). At one point they are
saying they have automated RTL, but not for everything?? At another point
they dismiss fully automated RTL as overkill. What's the story? Claim
to reduce memory power by 40% but just identify something that designer
should have done anyway? Claim to have worked with Virage for memory
power stuff. I couldn't verify this with Virage.
- [ An Anon Engineer ]
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Biggest lie? "UPF and CPF are converging." Yeah, asymptotically.
- John Donovan of Low-PowerDesign.com
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Real, actual in-tool support for UPF is a joke.
- [ An Anon Engineer ]
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The biggest lie I heard came from a Cadence representative: "Cadence has
always supported industry standards." It wasn't too long ago that they
were trying to kill off System Verilog and going out of their way to say
they do not support it.
- [ An Anon Engineer ]
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I think the big lie is on ESL. There were some small new companies there
with lot of talk, but no customer. (I mean real customer.)
- [ An Anon Engineer ]
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Biggest lie? The C level ESL train has left the station (Mentor free
lunch talk). Perhaps the bullet train has left in Japan, and the Eurail
is pulling out in Europe, but in the states no one is at the station
(except maybe TI??) So calling 'All Aboard' is premature.
- [ An Anon Engineer ]
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The biggest lie is easily Cadence still showing their "First Encounter"
placement estimation tool. Their AE said they do sell. Can we believe
this? This is like still fixing Y2K.
- [ An Anon Engineer ]
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Biggest lie? Still no real full custom offering from Synopsys that I saw.
- Paul Egan of CSR
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Biggest Lie: SystemC synthesis will improve my verification performance.
Since I typically need a cycle acurate model to find many of my bugs, I
do not believe a cycle accurate C model will perform any better than a
cycle acurate Verilog model.
As a note: I understand why C-synthesis might be appealing for blocks that
have a underlying algorithm, that can be easily described in C and then
synthesized to different performance points, but it seems to me that there
needs to be some standardization on how the implementation instructions
are passed to the synthesis engine.
- [ An Anon Engineer ]
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I can't even count the number of people at companies like Mentor, Xilinx,
Altera, Synopsys, Sonics, Calypto, and TSMC who claim that the industry is
just in a cyclical downturn and that we are on the verge of "fixing the
industry" once the economy turns around.
- [ An Anon Engineer ]
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The Altera and Xilinx folks claim that FPGA is positioned to take over
ASIC. Sadly, they are just going to take slightly larger share (%) of the
FPGA+ASIC declining market. If they do not provide more comprehensive
migration solutions from FPGA to Structured or full ASIC, then they will
not capture significant revenues from the ASIC TAM.
- [ An Anon Engineer ]
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The biggest lie I heard at DAC was from Synopsys, when they claimed to me
that their XA circuit is within 1% of accuracy of HSPICE, and then passes
this off as "SPICE-accurate". I've had similar experiences with Cadence
Spectre Turbo, and results from both XA and Spectre Turbo have revealed
that they're anything but "SPICE-accurate". The results from these tools
are such that both tools are completely scorned by our analog/RF designers
for any serious use.
- [ An Anon Engineer ]
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Biggest LIEs
Oasys: It seems that Joe Castello name is not enough, you need a product
to support your statements, too. I don't know where they stand and not
sure even if they were showing demo.
Achilles Systems: I was hopeful with pre-DAC interview, but tool is
sublime and very basic. Even my verification team can develop better
tools then them. I am surprised that they are expecting to sell this
tool for $$.
I didn't pay attention to Mentor, Cadence, Synopsys and TSMC booths.
Nothing real happening there...
- [ An Anon Engineer ]
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Worst. There were a lot of IP and other EDA tool accessories. Their cost
when asked were very expensive ($100K) and they only serviced a portion of
the IC design and simulation process. One booth offered characterization
of your devices basically indicated that you do most of the work then plug
it into their $100K software to generate the parametrics. Way over priced
for me doing most of the work.
- [ An Anon Engineer ]
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Biggest lie? Denali thanked me for coming to their DAC party. Either
somebody else lied, or Denali was confused. With travel budgets as they
are, I've not set foot in the US for a few years now.
- David Talbot of Aptina (UK) Limited
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