( DAC 09 Item 11 ) ---------------------------------------------- [12/11/09]

Subject: Silicon Frontline, Orora Arana, Analog Rails

ANALOG STUFF: For extraction, Silicon Frontline seems to be the favored son
at this last DAC.  For the elusive "analog synthesis" beast, there's user
comments here for Orora, Mephisto, and Ansyn.  Go to the Magma part in this
report for the Titan comments.

     What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
     you saw at DAC this year?  WHY where they interesting to you?

         ----    ----    ----    ----    ----    ----   ----

  The most interesting specific tool I saw at DAC this year was Silicon
  Frontline's F3D parasitic extraction software.  Parasitic extraction is
  not exactly a sexy topic, but when you make the insane claim that you
  can extract a full chip with 3D field solver accuracy in a reasonable
  amount of time, I had to see what they had to offer.

  After listening through their marketing presentation, I wish we could
  do a full blown evaluation on this product - if their claims are true,
  it would be the first significant innovation in this area for a while,
  as just about every other parasitic extractor uses a pattern matching
  algorithm versus what is effectively a statistically based in-situ
  field solver.  But the fact that they appear to have been qualified
  with TSMC and UMC seems to imply their technology is not bunk.  Last
  time I got this excited about a product at DAC was three years ago.

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Silicon Frontline was formed by a team from Nassda that had developed the
  advanced post-layout analysis capabilities which set HSIM-Plus apart form
  other Fast-SPICE solutions.  (I know, because I emphasized and promoted
  that differentiation while I was the HSIM product marketing manager.)  It
  is a differentiation which Synopsys still gets to enjoy today.

  I met with Dermott Lynch, Silicon Frontline's VP of Sales, to discuss the
  company's new solutions for 3D extraction (which made Gary Smith's "What
  to See" at DAC list).  The company claims to provide near-3D RC extraction
  accuracy with something approaching 2D performance.

  The cumulative experience of the ex-Nassda team in how to manage large
  parasitic databases, and to optimize analysis of effects in signal and
  power nets, does make them a company to watch.

      - Michael Demler of Digdia

         ----    ----    ----    ----    ----    ----   ----

  Silicon Frontline products: F3D & R3D for fast 3D extraction and for 3D
  extraction and analysis of large resistive structures like power devices.

      - Pierluigi Daglio of STmicroelectronics

         ----    ----    ----    ----    ----    ----   ----

  SKILLCAD's tool suite seemed to be a bunch of really useful widgets that
  fill in some of the gaps in the Virtuoso feature set and what the
  foundry PDKs provide.

  Silicon Frontline's extractor looks very interesting.  Another one to
  watch closely.

  I liked having CST there this year.  I hope they return.

      - Grego Sanguinetti of Tektronix

         ----    ----    ----    ----    ----    ----   ----

  Number 1 impressive tool is Arana from Orora.

  Number 2 is the emulator from EVE.

  I don't have number 3 or 4, unfortunately.

      - Harry Wang of Actel

         ----    ----    ----    ----    ----    ----   ----

  Arana from Orora
  Virtuoso, Ultrasim and AMSDesigner from Cadence
  Helix from Ciranova
  ??? from Analog Rails  (Cant find the tool name)

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Orora Arana

  Analog behavioral modeling tool.  It automatically extracts "intelligent
  behavioral models" from circuit netlist.  Claims 100x - 1000x faster than
  SPICE.  No testbench needed to generate behavioral models.  Also generates
  formal analog assertions.  Arche does hier characterization and ERC across
  PVT corners.  Arsyn does hier opto and yield improvement.  Cadence ADE.

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Berkeley Design Automation - Analog/RF FastSPICE.  The new solver
  algorithms promise the ability to take on RF circuit analyses of much
  larger circuits, which is *always* music to the ears of our analog
  designers.  That company built up a solid reputation in our team for
  the quality of their simulators.

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Mephisto Design Automation

  Mephisto is another recent entrant into the latest generation of analog
  optimization vendors.  In the last generation there was Neolinear,
  Antrim, Analog Design Automation, Barcelona.  Now we have Magma, Orora,
  Mephisto, MunEDA, Ansyn.  There just wasn't time to see them all.

  I was interested to check out Mephisto, since they are attempting to
  commercialize technology developed under Prof. Georges Gielen at KU Leuven
  in Belgium.  Georges was an adviser to us at Antrim, and I enjoyed
  visiting with his students on several occasions.  Unfortunately, after
  another early morning drive to San Francisco, this meeting never
  happened as I found myself standing in an empty booth.  You've got to get
  more organized guys!  So, I can only attempt to interpret the product
  descriptions on Mephisto's website.  They claim to be able to do "sizing
  from scratch", which is a more aggressive claim than most competitors.
  It is very difficult and inefficient, and often impossible, to start an
  optimization with a completely un-parameterized circuit.  (We patented
  methods to address this at Antrim.)  It actually appears that their
  technology for verification is more valuable than the tools for
  optimization.

  Mephisto also claims to have "patent-pending technology" (but I couldn't
  find any pending claims on http://www.blogger.com/www.upsto.gov) that
  "allows designers to capture and solve complex design problems at multiple
  abstraction levels simultaneously".  This is also something we developed
  at Antrim, to move beyond brute-force SPICE simulation-based optimization
  algorithms.  To avert any potential conflict, I advise checking out the
  Antrim patents, which now belong to Cadence.

      - Michael Demler of Digdia

         ----    ----    ----    ----    ----    ----   ----

  Analog Rails - correct by design analog design tools (down to the layout
  level).  Useful for mixed A-D type designs with "small-A" requirements
  so that "dirty" analog front-ends can be designed into very quickly into
  large digital "back-end" cores for heavy post processing!

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Teklatech - FloorDirector

  Tool used for reducing the voltage noise at the system level through
  design optimization (no cost added).

      - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

  Meeting with Ansyn

  Ansyn was the 3rd analog optimization company on my agenda, catching my
  eye for their claim to perform "Analog Circuit Synthesis at System Level".
  This was the company's 1st time at DAC, after spinning off technology
  developed at Linkoping University in Sweden in 2006.

  I met with Emil Hjalmarson, PhD and CEO of Ansyn.  The discussion with
  Ansyn turned out to be, totally by chance, the highlight of DAC for me.
  As I was discussing Ansyn's approach to simulation-based optimization
  with Emil, I could not see behind me as a gentleman apologized for
  interrupting as he grabbed some literature from the rack in the corner
  of the tiny booth.  Emil appeared to be especially concerned about who
  the stranger was, as he asked us if we minded him listening in to our
  conversation.  He identified himself. "I'm Andrei Vladimirescu."  If you
  know SPICE, you know Prof. Andrei Vladimirescu, since he co-wrote the
  1st successful version: SPICE-2.  He also authored "The SPICE Book".

  This made for a very stimulating impromptu conversation as we discussed
  the pros and cons of integrating an optimizer into the core of a new 
  simulator, as Ansyn has chosen to do.  (We debated this very same issue
  when we were developing our product plan at Antrim.)  Prof. Vladimirescu
  rightly pointed out that achieving market acceptance and foundry
  endorsement for a new simulator is a major challenge, and can be an
  insurmountable obstacle to success.  On the other hand, having the
  optimizer wrapped around an existing commercial simulator means suffering
  huge performance penalties.  At Antrim, I had argued for the deeply
  embedded approach, so that we could build a revolutionary system that
  would be designed not so much for simulation as for optimization, by
  allowing the "synthesizer" to directly alter the matrix dynamically.
  Well, R&D would have none of that, and instead we ended up building
  the worst of both worlds.  We had a new proprietary simulator AND, in
  order to accelerate that development as a stand-alone product, we still
  wrapped the optimizer around the outside.

  For optimization, Ansyn's tool can potentially achieve higher performance
  than other solutions.  They are also taking advantage of mutli-core
  processing, which has become popular for accelerating traditional SPICE
  simulators.  I don't see any realization at this point to back up the
  provocative "synthesis" claim, but it will we interesting to see if Ansyn
  comes away from their 1st DAC visit with a desire to jump into the EDA
  fray, or stay local in the much smaller European market.

      - Michael Demler of Digdia
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