( DAC 09 Item 8 ) ----------------------------------------------- [12/11/09]
Subject: Extreme GoldTime and Tiempo
FREAKS & WINDMILLS: As a chip designer, I have to admit I love a good tweak
technology that comes out of left field -- for example designing a real life
production chip -- that's entirely in asynchronous logic! Yea, I know it's
like building canoes out of cement; but it's still a hoot to try. And the
same can be said of "Davids" trying to take on Goliath. God Bless them!
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
---- ---- ---- ---- ---- ---- ----
Tiempo. It's a French company new to DAC. Tiempo claims to have an
asynchronous synthesis tool for System Verilog transaction-level designs.
The benefit to the ASIC designer; ultra-low power designs, dynamic power
IP, designs resistant to large PVT variations, reduced noise, reduced
electromagnetic emission and susceptibility, etc.
I didn't get verify the capabilities of the tool at their booth, but they
did have an impressive demo. They have several asynchronous IPs and were
showing a demo of their 16-bit asynchronous microcontroller core. They
could dynamically vary the supply voltage and the power and MIPS varied
accordingly. One application for an ultra-low power micro-controller
might be power sequencing and control in a low power mobile ASIC.
- Edward Paluch of Paluch & Associates, Inc.
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GoldTime from Extreme DA -- A worthy competitor for PrimeTime at last?
They claim to match PT's accuracy within 3%, be at least 3X faster than
PT-SI, *and* have a memory footprint which would fit on a smaller box
than PT does. For larger designs, this might be a winning combo. Their
slide on customer numbers seemed quite impressive, not just on the
number of customers, but also on what those customers are seeing. Will
be actively looking out for these guys.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended one suite demo in the hotel from Elastix. It sounds like they
have nice tool/services. The cool part was that they had a test chip.
- Djavad Amiri of AutoESL
---- ---- ---- ---- ---- ---- ----
EnterPoint - potentially flexible customer specific FPGA based emulation
and simulation boards. Could be useful for bringing up our RTOS based
system design before resorting to full custom IC implementation.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Questa UPF 2.0 support.
Mentor claims Questa low power verification is production ready. With
UPF 2.0 support their tools support complete low power verification for
complex (45nm/28nm) multi-power domains designs. Good stuff if true.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Mentor's new die + package + PCB codesign platform.
There are two platforms today for die/pkg/PCB co-design:
1. Cadence Sip
2. New Mentor solution
40nm/32nm Sip (system-in-package), Pop (package-on-package) and TSS/TSV
requires an integrated solution for system co-design. This is one of
the complete solutions.
- [ An Anon Engineer ]
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