( DAC 09 Item 7 ) ----------------------------------------------- [12/11/09]
Subject: Magma Talus/Vortex/Titan/Quartz/Hydra/FineSim
HELL YEAR: When Rajeev writes his private "History of Magma", 2009 is going
to go down down as LAVA's Hell Year. What used to be a spacious 20 room
DAC suite swimming with users and activity and buzz and bravado, in 2009,
turned into a sad little single room booth. One user's comment said it all:
I heard people were taking cell phone pics of the Magma booth, and
sending them to other Magma people asking "what happened?".
It's been ugly. They had tech problems migrating customers from BlastFusion
to Talus, Quartz couldn't read Calibre libs, Hydra and Titan were new and
had beta bugs. Magma's P&R marketshare dropped to 20%. Layoffs came.
DAC 2009 was the height of Magma's low.
Yet even at this harshest of DACs, Magma had a base of hardcore loyal users
visiting them who were pleased with the technology they were seeing. The
recent ESNUGs also confirmed that Magma had cleaned up its act when the
hands-on users directly reported that Talus Vortex, Titan, FineSim, Hydra,
Talus Design, and Quartz were all now happy and healthy and working:
ESNUG 479 #3 Quartz did 1.5 B transistor sign-off DRC in 4 hours
ESNUG 479 #6 Magma Talus Vortex is a big step up from BlastFusion
ESNUG 480 #4 TSMC confirms Titan uses mins vs. weeks for 2nd chip
ESNUG 481 #6 Cadence Spectre vs Magma FineSim benchmark data
ESNUG 482 #9 ECOs, benchmarks, Talus Design (Blast Create II)
ESNUG 483 #2 We dumped Mentor Calibre for Magma Quartz DRC/LVS
ESNUG 483 #6 Benchmarks of Magma Talus from 1.0.86 to 1.0.91-beta
ESNUG 483 #9 We saved 14 man-weeks using Magma Hydra floorplanning
"Their tools are now all fixed," agrees Gary Smith. "Now the question is
can Magma win the customers back."
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
---- ---- ---- ---- ---- ---- ----
I am impressed with the runtime improvements in Magma Talus. I've used
the new version and new commands and found that it closes timing and DRC's
much faster now. I would still like to see how MCMM solution works, I
have not checked it out yet.
- Truong Hoang of Qualcomm
---- ---- ---- ---- ---- ---- ----
Some input from the Magma Hydra floorplanner DAC presentation:
Hydra's full-chip capacity seems impressive. New prototyping commands
like "run optimize coarse", "run optimize global", "run optimize budget"
seem to give better quality estimated congestion and timing.
Hierarchical pin optimization seems to be more efficient. Several
new commands are available: an interesting one is "fix congestion".
Reference flow for Hydra is available for full-chip prototyping.
- [ An Anon Engineer ]
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Magma's Quartz DRC and LVS at DAC:
- Qualified by TSMC, UMC, Chartered, IBM, Samsung, SMIC.
- Magma claims it's 3X faster over competition (Mentor Calibre,
Synopys Hercules/ICV) in customer benchmarks.
- Very efficient distributed processing with very little
overhead (linear scaling).
- Tcl programming input capabilities for input, runsets, and output.
- Easy shorts finding features, LVS debug.
- Incremental DRC capabilities.
- Automatic Calibre runset conversion, Hercules conversion not yet
available or not yet in production.
- Some runset optimization may be needed for best performance.
In general, if a customer is using a major foundry which can provide
DRC/LVS runsets for Calibre or Hercules, there is no reason NOT to
look at what Quartz DRC/LVS can offer.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I went to the Titan demo to find out more about the tool. What I learned:
(a) schematic and layout capture GUI is very similar to Cadence's
(b) can easily exchange/transfer database back and forth with Talus
(c) claims to be able to direct read Cadence OA database
Since we already use Quartz and Talus, it was nice to see speed updates
Magma had made in the new versions.
- Norman Chan of Rambus
---- ---- ---- ---- ---- ---- ----
Magma Titan ADX because its new model-based approach allows circuit
optimization and porting in a shorter time with respect to the traditional
simulation-based techniques. It seems to shorten the analog design
process from weeks to days also reducing power and area. It should also
allow a rapid design exploration as well as design specs retargeting and
process migration for both schematic and layout views.
- Pierluigi Daglio of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
Titan ADX: Take the Guesswork Out of Analog Design
Finally (such a long day, I had to skip the Denali party), I ended the 2nd
day of DAC with a presentation on Magma's Titan ADX: Analog Design
Accelerator. There was a noticeable increase in activity at this year's
DAC associated with analog circuit optimization, which is the function of
the ACX tool in Titan. (Along with AVP for virtual prototype - a physical
placement, and ALX - a layout accelerator). This is a subject of interest
to me going back to my time at Antrim Design Systems, where we had the
crazy idea of developing analog synthesis. (We did make a lot of progress
before the wheels fell off, and were awarded 5 patents - which now belong
to Cadence).
Titan ACX is built from technology acquired from Mar Hershenson's Sabio
Labs, which was itself a rebirth of the first attempt to commercialize
this technology at Barcelona Design. Magma describes ACX as a tool that
uses analog functional models built from process-independent equations to
optimize blocks such as PLLs, bandgaps, and ADCs. The key difference from
earlier positioning is that a user starts with an existing circuit, and
then optimizes for a few objectives, such as area or power, and not to
"synthesize" the entire circuit. That seems more reasonable, but the
other constraint with this approach is that the circuit much match the
model - which was a problem with the "geometric programming" methodology
at Barcelona.
It takes much longer to create and validate a new program of equations
than to actually have an engineer design the circuit. So, ACX would best
be applied to analog block re-use and tuning. However, many circuits need
to be re-architected to work at lower voltages in scaled processes, so at
that point the model template and equations would need to be changed as
well. That is a different skill than circuit design, which is why most
attempts at analog synthesis have been limited to linear circuits that can
be described algorithmically.
- Michael Demler of Digdia
---- ---- ---- ---- ---- ---- ----
I saw at DAC an introduction to the Magma FineSim simulator which was
targeted towards a technical oriented audience. I learned that the
FineSim simulator core is natively built for parallelization using
multiple CPUs "resulting in a highly scalable solution." They claimed
that the simulator runtime almost linearly scales with the number of
CPUs, and with SPICE accuracy. At the same time Magma claimed that
there is a dramatic capacity increase for SPICE simulations, enabling
precise SPICE-accurate simulations not possible before or with other
state of the art circuit simulators.
FineSim Pro adds the Fast-SPICE part of the simulation engine and
appears to have easy to use speed/accuracy controls.
Assuming it works as advertised, it could be well ahead of competitive
tools when it comes to pure SPICE and Fast-SPICE circuit simulation in
terms of speed, accuracy and capacity. Assuming...
- Olaf Zinke, co-author of "The Designer's Guide to Verilog-AMS"
---- ---- ---- ---- ---- ---- ----
Here's the "pluses" for Magma SiliconSmart that I found compared to other
characterization tools. (My comments are based from documentation; we
need to do an eval.)
1. Automatic function recognition. With other tools, you need to
manually write the function for the DUT.
2. CCS/ECSM timing, power and noise model. Other tools don't seem
to provide CCS noise, CCS power.
3. IBIS 4.1 (other tools don't provide an IBIS model)
4. Dependent setup and hold. Traditionally setup/hold timing in
our .lib files are independent.
That means setup timing is measured when the hold timing is big enough
and the hold timing is measured when the setup timing is big enough.
Considered independently, these two checks can result in a negative
pulse where data is not allowed to change.
- Jun Li of Trident Microsystems
---- ---- ---- ---- ---- ---- ----
Magma - a new compaction engine to fight against VLM from Cadence and the
last independent vendor in migration, Sagantec.
- Coming up with a very efficient tool who learns from one compaction to
another and performs incremental "redo"
- Runs in minutes with 100% DFM solved
- Respects device rules and modify the PCELLS to new process limitations;
max WIDTH
This tool combined with the new Magma router and the Titan engines should
pose a serious challenge to Cadence Virtuoso platform
- Dan Clein, author of "CMOS IC Layout Concepts"
---- ---- ---- ---- ---- ---- ----
I'm a graduate student and have very little industry experience. I went
to this SiliconSmart demo not to assess the tool but to pick up info about
library characterization.
They seemed to have a very vast customer list. Room was hard to find.
- [ An Anon Engineering Grad Student ]
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