( DAC 09 Item 6 ) ----------------------------------------------- [12/11/09]
Subject: Apache RedHawk/Totem/Sentinel and Sequence PowerArtist
HAPPY MARRIAGE: At DAC the rumor mill went nuts that Apache was aquiring
Sequence. It took 2 months for that rumor to turn out to be true. One
unconfirmed rumor was this wedding saved Sequence after it had gone through
"16-18% lay-offs ... across all the divisions including R&D". This union
reinforces Apache's sweet majority marketshare vs. CDNS in low power design.
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
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1. Sequence PowerArtist-XP: Analyzes RTL for total power reduction.
Provides automated debugging of power wastage. It infers clock gating
and clock trees and handles block level clock gating. It can make the
RTL changes for power improvements. Sequence has been continually
improving their offering in early power analysis space and Power Artist
has no competition in the Industry.
- Anil Gundurao of Cypress Semiconductor
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We want to reduce the power on our chips while keeping the throughput
same. PowerArtist seems to help us in that direction. Based on what
I saw, Sequence came out with a more comprehensive story by tying
together all their optimization (clock, memory, data) features in one
place and help visualize power at the RTL level (early in the flow).
- [ An Anon Engineer ]
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We use Apache's RedHawk for analyzing the power grid on a pretty large
SoC design using the static and dynamic analysis flows.
This year I attended some of their presentations. They talked about
their NX technology which they claim to deliver considerable run-time
and capacity. What I found interesting was RedHawk Explorer which lets
you to do data integrity and result analysis. One of the struggles I
have with power analysis in general is understanding the specific
reasons behind a specific dynamic voltage drop. Apache seems to have
done a good job in integrating analysis and data mining in a nice
interface. I am interested to use this on our designs going forward.
I should also add that Apache's support continues to be the best I have
seen among all of the EDA vendors we use. Power analysis and
particularly dynamic power analysis is a difficult topic and Apache's
AEs help us any time day or night to go through the run and results.
- Sumbal Rafiq of AMCC
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Redhawk-Explorer is a promising new capability added to Redhawk where-by
it gives user the ability to sanitize the input data and find the root
cause for design weakness causing high dynamic drop in the design,
whether it is coming from high simultaneous switching, or low decap or
high clock buffer clustering or high package inductance etc. This will
help in reducing the time required to debug IR drop issues. I got a
sneak peak during DAC and looking forward to use it soon.
- [ An Anon Engineer ]
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b. RedHawk Explorer from Apache
This new addition to the Redhawk IR-drop analysis tool appears to be
geared towards improving productivity, which would be very welcome.
Experienced users might be skeptical, but I see this being a huge
time-saver for new users of their tools, even experienced engineers
(whose managers told them to take over somebody else's work.) ;)
The GUI is nicely laid out, with intuitive tabs. Particularly of
interest is its data integrity check (garbage in = garbage out)
and hot-spot feature - this will certainly help debug issues much
faster. To boot, no extra license (something you don't hear too
often!) I look forward to trying it out on one of our blocks.
- [ An Anon Engineer ]
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The best presentation I attended was Apache RedHawk. They're not like
some other EDA companies, only showing marketing slides. They gave
full technical detail and methodology flow, etc.
Their GUI shows plenty of information of the design and help to improve
the power design from up front.
I hope Sentinel can help us in that area, too.
- [ An Anon Engineer ]
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1. Apache Totem/Sentinel
2. Oasys synthesis tools
3. Entasys early floorplaning tool
4. Tela Innovations
- [ An Anon Engineer ]
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Apache Totem because it offers a full chip power and noise integrity
analysis for AMS chips containing analog blocks.
It consists of two main products with different capabilities:
- Totem-MMX, a transistor level IR dynamic voltage drop analysis tool
for power & ground network at IP and full-chip level. It also
supports IP model generation and signal EM validation.
- Totem-SE, a full-chip tool for simulating the substrate noise
injection and coupling through the on-die power & ground network.
It enables designers to account for the impact associated with global
coupling of power & ground noise, substrate noise, and package capacitive
and inductive noise on their designs.
- Pierluigi Daglio of STmicroelectronics
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2. Apache Totem: Apache has been focused on ASIC designs with Redhawk.
With Totem they extend their power grid signoff to the custom space.
They can handle huge capacity and showed 200+ M transistor designs
analyzed within a day. Totem can crossprobe to Virtuoso and create IP
power models. This tool will make Apache's power grid solution more
comprehensive. They continue to solidify their lead in this space.
- Anil Gundurao of Cypress Semiconductor
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Apache's EMI reduction capabilities
- [ An Anon Engineer ]
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I was impressed with Apache's aggressive solution space. They will be
one to watch for the SIC, MCM and module crowd. Their Chip Power Model
(CPM) looks like a good strategy, but us RF-IC wackos would probably
need to be able to monkey with it directly.
- Grego Sanguinetti of Tektronix
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Apache. I sat for demos on the Sentinel suite of products and their
chip power modeling (CPM).
Being a system house, we verify the power integrity of the cards that
we designed. The ASICs on our cards are high on power consumption.
Without good models to represent their characteristics we would have
to depend on heuristic models. With the CPM we get two benefits:
- our ASIC vendor performs detailed on-die level analysis and
- we can get a model representing the die current/time and die
power parasitic.
Sentinel and Redhawk enables an integrated die, pkg, PCB analysis.
- [ An Anon Engineer ]
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Cadence Low Power solution uses dual-flops and pulse latches to reduce
clock power. Both are promising techniques as these can be automated
in their existing P&R flow. I was particularly interested in dual-flop
as it gives some power savings (10-15%) out of the box - the current
Cadence flow has not changed except adding few extra commands.
We are planning to work with Cadence to implement this in our next
generation products. Pulse latch implementation might be much more
involved, so we leave that for future.
- [ An Anon Engineer ]
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The Low Power demo at the Cadence suite was interesting, particularly the
way all their tools knew what each other was doing in the power domains.
Some of the automation features in EDI System were pretty useful, like
determining how many power switches are needed for a given design. I can
see a few useful applications of this.
One catchy item in that demo was dual flops and pulse latch technology;
seems like an innovative way of reducing power by modifying the registers
in the design.
- [ An Anon Engineer ]
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