( DAC 09 Item 4 ) ----------------------------------------------- [12/11/09]
Subject: Mentor Olympus-Calibre and AtopTech Aprisia
THE BATTLE AT 32 NM: It was odd. I found it was the backend transistor
physics nerds who were chatting up Olympus and Atoptech -- even though these
are DIGITAL layout tools. "That's because these tools are fighting for the
32 nm node where physics rule. They both do extremely well at 32 nm," said
Gary Smith. "Atoptech use seems to be more general. What I'm seeing for
Olympus users is that they take Synopsys designs and rerun them. They're
not using Olympus as a 'me, too' check tool, but more as a turbo charger
for designs that already have gone through IC Compiler. Both Atoptech and
Olympus are gaining ground in the market place because of 32 nm effects."
Also, the tight integration between Olympus and Calibre was a win with the
users; particularly for the speedy automatic fixing of violations.
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
---- ---- ---- ---- ---- ---- ----
3. Atoptech Aprisia: This tool is built to handle design hierarchies
efficiently. Customers seem to be adopting this and had good feedback
on QoR. Excellent correlation in timing to PrimeTime and clean DRC/LVS
is strong points seen by users. I think Atoptech will take some market
share from the others.
- Anil Gundurao of Cypress Semiconductor
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CiraNova Analog device placer - represents the first truly credible
offering I have seen in 25 years.
Atoptech P&R: They seem to be solving the normal timing closure problems
in a novel way.
MicroLogic: Real time DRC - Really good understanding of how to show
DRM, DFM & recommended DRC rules.
MicroMagic (I think - I can't find their contact details): 3D Terabyte
sized database viewer. Very useful to us for 3D visualisation of
RF & cross section layouts.
- Paul Egan of CSR
---- ---- ---- ---- ---- ---- ----
1) Mentor Circuit Limited Yield (CLY)
2) Mentor Calibre DFM
3) Mentor PERC
4) AtopTech Aprisa
In general, Mentor's presentations are very solid as usual. I especially
enjoyed 1 & 2. However, I got a strong impression of the capabilities
of Aprisa.
- Fred Ki of Actel
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One interesting demo that I saw was Mentor's Olympus-Calibre. The user
can verify and optimize DRC, LVS, CMP metal fill and LFD with sign-off
accuracy without having to leave Olympus. Being able to switch between
LEF and GDS view also helps in debugging. There is supposedly a dynamic
window sizing capability in fixing DRC with fast TAT and minimal
timing impact.
Question is when to turn on Calibre? If there are too many violations,
I think the TAT might be longer than Olympus native engines. But the
fact that user does not have to rely on file interface between the tools
should give the current Olympus users some productivity benefits.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I am a chip designer and work in the bay area. Here are my notes from
the two Mentor Olympus demos that I saw at DAC:
"Project Janus" - this is a new capability that Mentor was pitching which
I found it quite interesting. They did a 10 minute presentation followed
by a 45 minute live demo. They invoked the actual Calibre DRC/LVS/DFM
engines inside Olympus and showed how they could do early signoff check.
More than the invocation, the feature that I liked was how the router was
able to interpret and automatically repair the identified violations and
ensuring that no new violations were created. In our current IC Compiler
flow, in spite of budgeting for surprises, we run into such physical
verification issues very very late in the flow and sometimes it takes
days to analyze and repair such violations. As you can imagine, such
late stage delays are very expensive and stressful and if this tool can
help me tapeout on time, I will take it.
Project "Tetris" - this was a demo focused on showcasing Mentor's low
power netlist-to-GDSII flow. Of all the features that they talked about,
the automatic module guided region creation/shaping, automatic macro
placement and MCMM-CTS were quite interesting. One challenge for any P&R
tool is its correlation with Star-RCXT/PrimeTime. Olympus also does not
have a magic bullet here.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended two Olympus suite demos (Mentor P&R):
Complete Netlist-to-GDSII flow. In this demo Mentor was touting their
next generation floorplanning technology "Project Tetris" in addition
to their chip finishing and eco flow capabilities. But for their large
capacity and MCMM technology, they seem to be on par with the other
offerings in the market.
Calibre and Olympus Integration. Demo on how users can run Calibre DRC
checks from within the Olympus environment. It was live making it quite
impressive and they showed how certain Calibre DRC, LVS, fill and litho
errors could be identified inside Olympus and *automatically* repaired
inside Olympus. They claim that any Calibre engine can now be invoked
in the inner loop of the router and this capability seems quite unique.
Post-DAC: we started an eval of this and initial results look promising.
At 40nm, I am not sure of litho, but Olympus integration with Calibre
LVS, fill and DRC definitely could improve our current manufacturing
closure flows.
- [ An Anon Engineer ]
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b. Mentor demoed Project Janus -- physical verification and closure
inside Olympus. Runs signoff quality DRC and litho checking internally
and uses the router to resolve errors in a nice closed loop. LVS debug
looked pretty cool also, with the ability to switch between LEF and GDS
views of macros to track down mismatches. Definitely could be a huge
productivity enhancer if it proves out.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended the Olympus demos at DAC this year and I thought that the
Olympus+Calibre (project Janus) demo in the Mentor Suite was impressive.
The ability to perform sign-off physical verification checks during
implementation is a very powerful feature for design engineers. Most of
our backend teams spend quite a bit of time iterating through the final
verification checks between P&R and physical verification tools. The
fact that they are able to automatically fix the violations (DRC/LVS)
and run sign-off checks on the fly will definitely help our backend
teams save cycles. They also showcased LFD as part of the implementation
which was also impressive. Now we're curious to see how much of this
is "real" vs. DAC demoware.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
1. Calibre PERC
2. Olympus-SoC
3. Calibre eqDRC
- Avadh Kumar Tibrawal of Cypress Semiconductors
---- ---- ---- ---- ---- ---- ----
1st - Calibre eqDRC. Since I am not a Calibre user, and I'm concerned
about yield, I find this topic is quite attractive to me.
2nd - AFS Nano (SPICE simulator), mini SPICE simulator from Berkeley,
claimed it's faster than HSPICE. Through benchmarking, we like it.
3rd - Calibre PERC. Since we have ESD issues, this also catches my eye.
- [ An Anon Engineer ]
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Accelicon MQA. May use it to help model developers. We need to check
SPICE models over an increasing number of parameters, and a commercial
tool could be worth the cost vs. enhancing our own scripting.
Mentor PERC. A new application for Calibre that we're starting to use.
- [ An Anon Engineer ]
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I liked that MicroLogic's visualDRC tool directly read the rules from
both Assura and Calibre. I also liked that it could present errors in
the same manner as regular DRC tools. It looked easy to setup and use.
I really like where Mentor is headed with their equation-based DRC.
David Abercrombie's presentation was really interesting. I hope the
fab vendors pay attention and take advantage of this.
- Grego Sanguinetti of Tektronix
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Need also to mention Micrologic-DA products: Visual DRC/LVS/NanoInteracRV
which seems to be very promising.
- Pierluigi Daglio of STmicroelectronics
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Calibre eqDRC: an equation based verification deck that will enable users
to fix ONLY errors that are impacting manufacturing, yield, etc. Today
DRC decks are more restricted than needed due to language limitation for
the verification tools -- so we will have to fix less errors.
- Dan Clein, author of "CMOS IC Layout Concepts"
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I went to the Mentor demos, what interested me the most was Calibre PERC.
This is because when I try to do some ERC checking using Calibre DRC
tools, even with support help from Mentor SupportNet, some of the ERC
checks are not easy to check because it works off the layout instead of
schematic. Look like PERC correct this weakness by working with an
extracted netlist. I was thinking when I have some time to have my
Mentor Account Manager arranged to have a PERC demo inside my company.
Most of the new tools are of no interest to me. We are an analog design
house that use 0.18u. For us, it is better to make us use the existing
tools more effectively than have new feature to solve a 45 nm problem.
This is why the PERC tools interest me.
- [ An Anon Engineer ]
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Mentor Calibre Yield Enhancer - Good to see CMP analysis and poly/metal
fill being integrated into a single tool, which would help improve the
quality of our tapeouts by moving CMP analysis further up the design
cycle and into the hands of the circuit and mask designers. However,
our chances of being able to look at this are remote, as our company's
"primary vendor" deal is with Synopsys.
- [ An Anon Engineer ]
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I found the DFM tools from Mentor Graphics to be interesting. Also
their perspective on this space.
- [ An Anon Engineer ]
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In the Cadence demo, I saw how critical area, double via/contact, litho,
and CMP simulations could be invoked during place and route. Their demo
showed the fix of design hot spots with a user friendly interface.
I believe it is a big value to integrate place and route with hot spot
analysis tools and make P&R DFM aware. I saw this flow implemented for
the first time in Cadence DAC 2009 booth.
- Yuri Mitnick of Cortina Systems
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