( DAC 09 Item 3 ) ----------------------------------------------- [12/11/09]
Subject: Forte Cynthesizer, Calypto SLEC, AutoESL
A FALSE LEAD: In the prior Mentor Catapult C section of this report I noted
that Mentor seems to have the lead in C synthesis right now. Gary Smith
says that observation I make is misleading. "A large part of this new
market are engineers who want to take a specific algorithm and slam it into
hardware. Mentor obviously leads with those guys," warned Gary. "But Forte
concentrates on engineers who want to use C the same way they used Verilog
and Design Compiler. Those engineers like Forte. Also those customers are
demanding high quality control logic synthesis -- so the actual battle is
who's going to have the one tool that does both algorithmic AND control
logic synthesis well. That battle is anyone's game."
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
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We looked at taking our ESL design captured in SystemC and automatically
transferring it to silicon implementation in the most efficient way.
AutoESL AutoPilot -
I liked the fact that their demo included an actual FPGA implementation
so clients can see the tool put to actual use right on the spot. (I wish
the others would follow that model!!!).
Cadence "TLM-driven design" -
Cadence demos a design methodology that starts in SystemC TLM description
and carries it to implementation using their C-to-Silicon Compiler. I'm
a bit skeptical on their ability to inner connect all of these tools to
come up with one effective solution. Their progress is encouraging, but
we need to see more "non-academic" and "non-marketing" working tapeouts
to raise confidence in Cadence's solution.
Forte's Cynthesizer -
It is obvious that these guys have been doing it for some time now. Their
vast "real-life" SystemC to RTL experience does give them an edge over
Catapult C and the rest of the pack. (Also Forte has the most number of
tapeouts under their tool's belly).
- [ An Anon Engineer ]
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We evaluated Mentor's Catapult C and Forte's Cynthesizer. The results for
both tools were comparable to each other and, to a lessor degree, to
hand-coded RTL. (I expect their QOR compared to hand coded RTL will only
improve over the years.) As a result of the evaluation, I will be using
some flavor of High Level Synthesis on my next project, depending on
their final pricing.
I expect that with the "learning curve", the initial productivity for our
group will only be on par to hand-coded RTL. I expect significantly higher
productivity when retargeting the same design for a second use whether on
the same process or a different process and I expect at least a 2X
productivity speed-up for our next new design compared to hand-coded RTL.
- [ An Anon Engineer ]
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Forte design - ESL
Mathworks Matlab/Simulink - ESL tool, no need to know Verilog/VHDL
(or System Verilog)
- [ An Anon Engineer ]
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Forte's Cynthesizer tool was interesting. The current typical flow is
hand-coded Verilog RTL, but this high-level synthesis tool is good to
improve the performance and good to shorten the design cycle. Their
auto partitioning tool and the interface generation tool looked good.
- Jong-Burm Park of Korea Electronics Technology Institute
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Forte Cynthesizer: for its support for control and datapath, and a new
interface generator for custom interfaces that can be simulated before
synthesis.
- [ An Anon Engineer ]
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Calypto's Sequential Optimization Flow (PowerPro CG/SLEC 4.0). Cadence
should buy these guys before Synopsys pre-empts them.
- John Donovan of Low-PowerDesign.com
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Calypto PowerPro CG - fully automated power reduction through clock
gating (and MG, memory power reduction). I'd like my power reduction
to be quick and easy.
- [ An Anon Engineer ]
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I've been frustrated at the transaction-level modeling tools that are out
there, because most of them are either tied inexorably to one vendor's IP
or leave it to the user to develop all of the IP models from scratch.
Mentor's Vista Architect demo gave me hope we may be turning a corner...
The tool can provide stubs of code to aid in the development of TLM's for
complex IP, along with timing and power policies to help document design
intent. Plus, the included primitives may give one enough to start
designing a complex system without having to think through the authoring
of each part of the system. It also doesn't look like there's anything
stopping you from using another vendor's IP along with models we develop
in Vista, since the Vista-generated code is TLM-2.0 compatible.
I plan to spend the fall playing with it to see if it can do everything
that I hope it will.
- Rhett Davis of North Carolina State University
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Vista Architect seems to be a good tool for architectural design level;
for the phase where effort to optimize a complex system has the most
impact on a design. It also seems to work with CatapultC and Questa.
- [ An Anon Engineer ]
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