( DAC 09 Item 2 ) ----------------------------------------------- [12/11/09]
Subject: Mentor Catapult C
AN EARLY LEAD: In the so-called "high level synthesis" space (I put HLS in
quotes because that's really just a fancypants way of saying "C synthesis")
I see two indicators that Mentor Catapult C has the lead so far. The first
indicator is Gary Smith's numbers:
2008 ESL Synthesis Market: $29.5 million total
Mentor Catapult C ############################## $15.0 (51%)
Forte Cynthesizer ############ $5.9 (20%)
BlueSpec ######### $4.4 (15%)
Synfora PICO ######## $4.1 (14%)
The second indicator is not only that users commented more about Catapult C
than its rivals, they also *complained* more about CatapultC. This, oddly
enough, is good news for Mentor because it's evidence of engineers taking
the idea of using CatC *seriously*.
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
---- ---- ---- ---- ---- ---- ----
I attended a Mentor Catapult C ESL Synthesis demo at DAC in San Francisco
presented by Thomas Bollaert from Mentor. A description of the demo:
1. You code your design and a testbench in ANSI C++ to verify its intent.
2. You map the design into a particular technology, e.g. 90 nm, using
your existing libraries and other infrastructure bindings. You choose
the design frequency, define memory types e.g., RAM, ROM, define
interface control scheme, clocks, reset and handshake signals.
3. You set up your architectural constraints, dealing with ports, input
data, coefficients and output data used throughout your design.
4. You need to set up resource constraints next, followed by the schedule
step where you define scheduled operations, loops etc., to represent
the design at run time as it relates to its latency and throughput.
5. CatapultC synthesis generates the Verilog RTL code, followed by
verification and analysis steps to try to get the best implementation
given the various constraints listed above. You view the synthesized
design using Verilog or VHDL, or you can view its schematics.
My impression was very positive, especially in light of CatapultC customer
testimonies from Hitachi and STMicroelectronics earlier at DAC. Bollaert
addressed many of the audience's questions during the demo with a lot of
insight and consideration to specific customer needs; which bodes well for
the future enhancements of this product.
- Andrew Bartczak of Boston Scientific
---- ---- ---- ---- ---- ---- ----
My impression of the Mentor Catapult C Synthesis demo at DAC.
1. It's convenient for a data path design. Using C++ to develop at
the system level and quickly you have the silicon results for
time and area.
2. It shortens verification. No more dumping data from a C model
for RTL design check or for co-sim between RTL and C model.
3. However, for major control systems C++ seems not so advantageous.
4. RTL out of Catapult C synthesis is not readable. It becomes
harder for any downstream ECO process.
5. Say I'm right before going to gates and my design's algorithm has
a minor change -- how does Catapult C make minimum gate changes
for pre-silicon ECO?
6. What is the flow for post-silicon ECOs? Has it been tried?
7. How reliable is Catapult C for SLEC?
C synthesis is still a very new technology and has not quite been proven
in many silicon processes.
- Rachel Wei of RF Micro Devices
---- ---- ---- ---- ---- ---- ----
Mentor Catapult C's DAC presentation was good, but as a potential user,
I still see a few issues with it. Since our design is an ASIC flow, the
final ECOs, timing and power issues are critical. What is our design's
true golden database? We are still staying with our RTL flow.
- Fen-Yu Su of Bay Microsystems
---- ---- ---- ---- ---- ---- ----
After hearing that CatapultC is now effectively supporting control logic
as well as datapath synthesis, I decided to take another look at DAC. The
drawbacks which prevent me from migrating to a full C/C++ or SystemC-based
flow at this time.
1. Ideally, testbenches would be maintained in SystemC for rapid
simulation (and perhaps automatically converted to RTL). However,
SCV has serious limitations for complex constrained random testing.
We have a heavy investment in System Verilog (OVM and/or VMM based)
testbenches, which could conceivably still be used, but this defeats
the speed advantage of simulating in "C". Also, I do not consider
static, formal ABV tools to be a replacement.
2. I would not even consider using a C flow without adopting a
sequential equivalence checking tool. This is yet another expensive
tool I have to buy from a different vendor (Calypto).
3. The tool flow for making small engineering changes (ECO's) is not
well established. Is there one?
4. Tool budget (and engineering resources) are limited at this time,
given our projected chip starts.
I remain concerned that quality-of-results derived from designs developed
in ANSI C/C++ will not compare well to hand-coded RTL for our design area
(hardware accelerators for broadband communications), regardless of
claimed marketshare of CatapultC. I understand that high level synthesis
tools may perform better optimization with a less detailed specification,
but SystemC offers intermediate levels of refinement, e.g. loosely timed,
for flexibility.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I think Mentor's Catapult C is a step in the right direction, but there
are a large number of (technical) problems which face the chip design
industry, and I do not think that C is the Silver Bullet. The history of
this sort of technology is that you need a 10X improvement in some key
parameter in order to get people to change. There have been basically
two changes in chip design technology:
1. Going from rubylith to mini-computer-based CAD tools, circa 1980.
Schematic capture systems are the best example of the category.
2. Going from schematic tools to RTL sim and synthesis, circa 1990.
Catapult C simply does not represent a 10X revolutionary advance in the
technology. At best, it is an incremental improvement. At worse, it
is a "me too" product. I think that Mentor Catapult C is an above
average tool in this category. I'd give it a 5 out of 10, maybe a 6.
- Dave Chapman of Gold Mountain Consulting
---- ---- ---- ---- ---- ---- ----
We already own DC and NC-sim. Why should we dump money and engineering
time just to get yet another way to get to gates? Once all the HW hooks
are in your design's C, C's sim time is the same as NC-sim. Other than
money to Wally for duplicate ability, CatapultC is much ado about nothing.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Given that there is "only a 2-5% difference between CatapultC-generated
code and user-written code", and that Mentor guarantees that what is
written in C++ is what you get in RTL (SystemC does not provide such a
guarantee), CatapultC looks like a very interesting tool.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
We have too much invested in in-house legacy designs and IP (mostly in
Verilog with some in VHDL) to be messing around with bullshit C tools.
All Catapult C will do is buy us troubles. It's a negative investment;
it'll bring our company's design productivity DOWN not UP.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
The only thing I remember from the CatapultC DAC demo is that in addition
to datapath handling, Mentor has added support for control logic.
- Dan Halvarsson of ST-Ericsson
---- ---- ---- ---- ---- ---- ----
One advantage of CatapultC is its wide coverage of the ANSI C++ language,
apparently without compulsory Mentor-specific extensions. Other C tools
need specific language features that CatapultC doesn't need (at least for
now), yet Catapult synthesizes large parts of C++ that others don't.
Another advantage comes from its code-generation directives. Those appear
inline as pragmas in some other C-to-gates tools, but I understand that
Catapult keeps pragmas out of their code. This makes it easier to apply
different speed/space tradeoffs to different usages of the same C source.
When I asked, the presenters told me that some CatC directives allow array
interleaving across multiple RAM banks. This is just as important for
parallelizing memory accesses as loop unrolling directives are for
parallelizing arithmetic operations.
Gotchas: I know of C-to-gates tool that handles at least some function
pointers that can't be resolved at compile time, and Catapult appears to
lack that. Native floating point support isn't there either for Catapult,
even though fused datapaths for sequences of floating point operations
get good performance in rival C synthesis tools.
Catapult has one great feature that I've seen in only one other tool: the
ability to bind C-language pointer references to memories not under CatC's
control. The alternative is to recode every pointer or array reference,
read or write, as a call to some library function. Even with restrictions
(not entirely clear from their DAC demo), binding pointers to memory
interfaces makes for a much more natural C programming experience.
Compared to other C-to-gates tools, Catapult appears to have a relatively
large installed base and history of use. Popularity doesn't ensure
quality, of course. When talking about compilers, though, a wider user
base suggests that more different usages and off-the-wall corner cases
have been thrown at it. That increases the chance that any constructs I
would want to use have already been exercised by other users.
- Tom Vancourt of Altera
---- ---- ---- ---- ---- ---- ----
Catapult C
C synthesis starts to become a reality. This is a disruptive technology.
I was impressed with the capability of the tool and the integration in a
ASIC/FPGA design flow. If the number of users (designs) will double or
triple and the capability of the tool will be improved to include all the
low power techniques used today during RTL implementation C might become
the tool of choice for hardware accelerator design (video cores, graphic
cores, low power audio cores, etc).
The gains claimed in productivity and verification time are huge.
Also the quality can be much better than a traditional Verilog design
implementation. The designer can focus on architectural exploration and
optimization instead of one architecture.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I was already interested in HLS, but Cooley's column that HLS is here
just reinforced my interest. Since we are a Mentor house, it's only
natural that we'll look at CatapultC.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Mentor has improved their Catapult C synthesis tool. (We've been tracking
it.) Their DAC demo this year used an arbiter design to showcase their
new control logic synthesis capabilities. Nicely done. I have a comment
about its final RTL though -- it's completely structural and quite hard
for humans to read.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I went to Mentor's CatapultC presentation at DAC this year and it sounds
promising. We definitely will considering it for our next SOC.
- Benjamin Tran of Qualcomm
---- ---- ---- ---- ---- ---- ----
One of the most interesting tools at DAC this year was CatapultC. We've
been using it over the past couple of years to SoC hardware accelerators.
Its hierarchical and interface synthesis gave us decent QOR along with
high productivity compared to hand written RTL design. It hooks to
upstream Simulink and Matlab through C++ code plus downstream RTL power
estimation, SLEC, and RTL linting enabling an automated ESL design flow.
With control and low power synthesis being recently added, CatC is moving
towards being a full chip synthesis tool while still maintaining a high
level of design abstraction -- something Aart tried to do 10 years ago
with his failed Behavioral Compiler.
- [ An Anon Engineer ]
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