( DAC 09 Item 1 ) ----------------------------------------------- [12/11/09]
Subject: Oasys RealTime Designer vs. Synopsys DC-Topo
#$@%&*!!! -- Aart de Geus would have a heart attack if he knew the names of
his Tier 1 customers anonymously commenting here about Oasys. Sweet Jesus!
Oasys RealTime Designer is a younger, fleet-on-his-feet, more buff boxer
giving an elderly Synopsys a nasty kick in the company jewels (DC-Topo) and
it's not pretty. In the 20 years I've been covering Design Compiler, I've
never seen any rival tool get such an enthusiastic initial support from the
user base. This is the kind of nightmare tool that would have kept Aart
awake most nights if he hadn't diversified SNPS into other EDA spaces. Of
course, this all depends on Oasys delivering 100% on its initial promise and
not making any of the classic EDA start-up mistakes. Danger!, DC, danger!
What were the 1 or 2 or 3 or 4 INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?
---- ---- ---- ---- ---- ---- ----
I'm a senior technical staff member at IBM at the Burlington, VT campus.
I attended the Oasys synthesis demo at this year's DAC at the request of
a colleague. I was very impressed with the results that I saw despite
being somewhat of a skeptic with respect to demos. There was simply no
denying that they had a breakthrough algorithm that could be run on a
laptop in under 800 Mb of memory. Clearly Oasys has hit on a winner in
revitalizing synthesis as an interative rather than batch tool. I look
forward to seeing our customers adopt it.
- Tom Guzowski of IBM
---- ---- ---- ---- ---- ---- ----
Very impressive demo for Oasys. This is definitely a tool that we will
look into and recommend to our partners to try so that RTL/layout
iterations can be reduced.
- Yong Miao of Fujitsu Microelectronics America
---- ---- ---- ---- ---- ---- ----
The only interesting tool I saw at DAC this year was "Oasys". The way,
I see it is that in the past 10 years of so, many innovations happened in
the area of Design and Verification, but not much in the Implementation
space. What Oasys is doing is nothing short of innovation and I hope
they succeed. Apart from them I did not see anything stand out at DAC.
- Himanshu Bhatnagar of Mindspeed Technologies
---- ---- ---- ---- ---- ---- ----
Oasys Design Systems chip level synthesis. The idea of synthesizing,
and placing your 20M gate design with timing on your laptop while on
the plane coming back from DAC - several times - seems game changing.
If Oasys can integrate in the mainstream tools flows that is.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Another product I liked (but does not apply to me because I've turned
FPGA guy) is the synthesis tool from Oasys. If the real performance is
anything close to the demo, it's one fast synthesis flow.
- Dan Bezzant of Prequel, Inc.
---- ---- ---- ---- ---- ---- ----
Since I didn't use Oasys personally, I can only give my 2 cents from
the demo: Fastest logic synthesis I've seen for a long time that included
placement. Test case std cell utilization is ~70%. No CTS. No scan
insertion. Can't tell if the tool still will performs well at higher
utilization. I cannot assess the quality of placement nor routability.
With no direct exposure to the tool, I can see frontend designers using
RealTime Designer for quick check on quality of RTL and timing closure.
P&R engineers can use RealTime Designer to do "what if" experiments for
floorplan and macro placement.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
The other thing caught my attention is run time of Oasys chip synthesis
tool. They do not have complete QOR comparison (gate count, dynamic
power, leakage, die size etc) with other tools, but it looks promising.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
a. Oasys chip synthesis - high capacity, very fast synthesis tool
(multi-M inst designs in about an hour) with impressive physical
awareness (can output a seed placement). Showed physical partitioning
and module placement during synthesis considering interconnect length.
Claims speed-up comes with equal or better post-PNR QOR compared to
SNPS and CDNS synthesis tools. Looks very cool.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
A worthy Synopsys DC-Topo competitor? Oasys RealTime Designer may be it.
We were impressed with their demo at DAC. Physical synthesis with ability
to use a floorplan (if available; if not, Oasys can *generate* it) with
minimal runtime and memory requirements may just get users to migrate.
The GUI is very cleanly laid out, with a physical-implementation viewer
that can view color-coded congestion hotspots. The hierarchy browser has
cross-probing into your source RTL -- a nice touch. The runtime numbers
quoted (10X-20X faster than DC) were very impressive.
VHDL-support is not present yet, but is planned for the next release. We
look forward to engaging with Oasys, taking one of our real blocks through
the tool to see how well it perform and suit our needs.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I found Oasys RealTime Designer a good wake-up call to Design Compiler.
They're talking 2x-3x speed-up year over year. Oasys' approach to chip
synthesis rather than module synthesis is very appealing and the demo
seemed genuine enough. Lower convergence time with high quality was
their key message. Lack of System Verilog support will limit the usage
but it still holds good promise for the future.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
RealTime's performance and capacity enable it to digest a much larger
netlist than is possible with Design Compiler.
This could help *some* design teams but most will not be able to take
advantage as their synthesis flow is really built around having sections
of their design complete at *different* times. Basically we cannot
really take the entire design and synthesize it even if we wanted.
More interesting is how the placement (RTL partition + placement) and
synthesis are much more coupled. I am certain the number of FE->PD->FE
iterations would come down shortening design cycles.
I also like the ability to look at physical aspects of the design right
after synthesis. Designers can get feedback on their critical paths
with a lot more accuracy before the netlist goes thru the preliminary
floorplan or PD work.
I was impressed with the macro placement the demo showed during DAC.
It probably was somewhat massaged but nevertheless the way the mems were
aligned and grouped and the spacing between large objects looked good.
We are very interested in looking at this tool which should bring our
front end and back end design teams much closer.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I think Oasys RealTime is remarkable technology and to me it's easily the
most interesting tool at DAC this year.
We'll probably do some evaluations all the way through to physical design
to see how it turns out.
- [ An Anon Engineer ]
Subscribe to Newsletter
Send feedback to John... (He likes it!)
Index
Next->Item
|
|
