( DAC 04 Item 42 ) --------------------------------------------- [ 02/09/05 ]
Subject: Zenasis ZenTime & ZenCell
IN THE DNA -- Like biotechnology, the Zenasis approach to fixing timing in
your DC runs isn't in running DC longer; it's in tweaking the very cells
you use in your design. That is, ZenTime finds your worst paths and
optimizes the very transisters to speed up that path. ZenTime creates
new, faster custom cells (called ZenCells) which your P&R tool swaps in.
It's like dumping nitro in a stock car gas tank; dangerous but very fast.
Zenasis
Booth demo showed a product called ZenCell which is a transistor-level
library for gate-level standard cells. Their target audience is digital
designers who use logic synthesis, static timing, automatic place and
route, etc. and want more performance out of their gate-level design
methodology.
Zenasis replaces cells in your critical paths with ZenCells, which are
just optimized transistor-level digital cells with fewer levels of
logic and improved timing performance. (The traditional digital flow
abstracts only down to the gate-level, therefore missing improvements
at transistor-level digital logic. High-end full-custom IC designers
like an Intel microprocessor design team have long avoided logic
synthesis exactly for this reason, and instead have chosen to hand-craft
at the transistor level the structure and device sizes needed for
optimum performance.)
In the Zenasis booth demo one digital cell used 22 transistors from the
synthesis library, while ZenCells pared it down to just 13 transistors
which improved area and timing.
Zenasis has their own built-in SPICE simulator, but it wasn't clear how
they use their simulator in sizing transistors or if it is just used in
their static timing tool called ZenTime. They didn't talk about timing
across PVT corners.
The ZenCell technique is only applicable to digital cell design, and
has no application in the analog design world. It's possible that the
sizing techniques in Barcelona could improve the transistor sizing
that ZenCells use.
- Daniel Payne, Consultant
Zenasis sells tools that create new cells to speed your critical
path in a COT flow. They identify groups of cells in your critical
path and create a single new cell, which may involve reducing the
number of logic levels, sizing transistors, etc. Their tools
interact with Cadabra and Calibre to create layouts for the new
cluster cell. They claim a 10% to 15% speed increase. Their tools
work with Synopsys, Cadence and Magma; foundries they support
include TSMC and UMC.
Prolific does optimization for power, timing and (new this year)
signal integrity. It creates new cells with drive strengths that
are between the cells provided in your library. It combines cells
of different drive strengths and can combine cells from various
libraries (fast versus low power, for example) to create an optimal
cell for your situation.
- John Weiland of Intrinsix Corp.
The ZenCell demo did intrigued me enough to try them out. But due to
time pressure and work overload I didn't actually try the tool. I
would not mind looking at Zenasis if I had performance issue. I have
asked them to work with other groups, within Broadcom, having issues
meeting performance goal.
Strengths: ZenCells easy to integrate in Standard ASIC design flow.
Weakness: with 90 nm, ZenCells need to bring Power into equation.
I have also looked at Prolific ProTiming. I feel ProTiming is good for
engineers with a deficiency in their library and implementation flow.
For us there was very minimal performance improvement with a huge
amount of extra cells. Whereas, Zenasis can genuinely help you with
their ZenCell technology.
- Chetan Manharlal of Broadcom
I have only seen the demo and have not run the tool, so I don't have
detailed knowledge on what Zenasis can and cannot do.
Here's what Zenasis claimed it could do:
1) For a standard cell path A-B-C-D, each cell along the way has some
built-in margin. By combining cells into one (e.g. A-BC-D), then
uncertainty is reduced (there is no need for margin between B and C)
and the path as a whole can run faster.
2) If a specific context appears over and over in your design, but is
not covered in a typical cell library (e.g. a half adder where one
input was much later arriving than the other), then a special cell
could be designed for that function, rather than having Design
Compiler conjure up something on its own. The end result would
likely be both smaller and faster.
3) If some function is missing from a library, then the tool could
provide it.
As I understand it, ZenCell Factory is intended to work on all three
problems above, in an automated way. Over time, #3 will tend to
disappear as library companies add functionality, but #1 and #2 will
always exist (although better physical synthesis and/or tunable cells
can reduce them). The key to making this work in a methodology is
more than just generating a compatible layout, but also to have the
characterization for the new cells match the existing library (slews,
trip points, waveform assumptions, etc.), so that the delay numbers
are compatible.
The ZenCell Factory demo shows how their tool can use the same
characterization flow (including whatever tools are part of it --
custom characterization, CellRater, etc.) as was used for the rest
of the standard cells. They use automated layout generation, so
having the same DRC and DFM approach as was used for the original
cells is important. The devil is in the details here, so the demo
is a proof that a solution is possible, rather than a demonstration
that it actually exists.
As I understand it, Zenasis is trying to improve timing by finding
the minimum set of cells needed to improve delay with approaches
1-3, and then using an approach as close as practical to the process
that generated the original cell library in order to maximize
compatibility and minimize risk. The intelligence of the tools is
directed to finding the "ZenCells", and the generating/characterizing
them is meant to be standard.
- Rob Aitken of Artisan
I think the strength of ZenCells is seamless flow from ZenTime to final
cell characterization. The designer may now have new cells without
knowledge of cell implementation.
But I think, in some aspect, ZenCells is just workbench of other third
party tools (Kazam, Calibre, Star-RCXT, etc.) except characterization,
so it is vague to estimate the value of the tool. And it should be
customized for each customer's library environment because they use
different tools and cell characterization methods.
Another problem is sometimes Kazam's automatic layout fails then the
end-user doesn't know how to solve it.
Finally, the characterization should be faster. It does't support
distributed cell charac yet.
- Chul Rim of Samsung
In my opinion, ZenTime has way more potential than ProTiming because
it can do more than resizing of existing cells. The ability to create
a new transistor combination or structure can be critical to breaking
a performance bottleneck in many situations. That said, the custom
sizing portions of the algorithms are currently delivering most of the
automatic speedups we are getting. We are getting 10-20% speedups on
the combinational logic with 3-5% coming from new transistor structures.
ZenTime integrates smoothly into our flows with both Synopsys and
Cadence (PhysOpt/Astro and PKS/Nano). It essentially looks like an
incremental physical synthesis tool. We get best results running it
after initial physical synth and then running another incremental
physical synth afterwards. In this flow the output to route is the
same as a flow without ZenTime.
Strengths:
- Wide variety of transistor level optimization algorithms.
- Delivers good combinatorial logic speedup.
- Fits well in traditional physical synthesis flow.
- Good timing/area correlation of estimated new cells and final artwork.
Weaknesses:
- Maturity (we still regularly run into several design dependent bugs).
- Poor ability to handle some transistor structures (pass transistor)
except for sizing.
- Need for Cell factory (auto place and route, characterization, etc.)
to create final custom cell artwork and models.
- Capacity (LONG runtimes on anything over ~300K gates). Really meant
for block level optimization.
We have been using ZenTime for about 18 mo. We have used it to speed
up designs in both 130 and 90 nm.
- [ An Anon Engineer ]
Zenasis ZenTime: Great idea, but the setup just takes too long. They
depend too much on other EDA vendors. Basically unless you have tool
X, Y and Z, you wont get much benefit out of running ZenTime. Last
year, they also had issues with optimizing across hierarchies. Maybe
they solved it by now. I dont know.
- Himanshu Bhatnagar of Conexant
ZenTime is really useful but still yet not stable enough for full
production of SoC design. It may difficult to use by non-power ASIC
design team at this moment.
1) ZenTime will generate so many ZenCells which are important
cells for timing optimization of critical path. In best case,
I got about 23% timing improvement by using same process
technology that is similar to move one process technology
generation. This is really good.
2) But ZenTime generate so many new craft cells that called
ZenCell. Who can implement many ZenCells in your design on
quick turnaround time? Not so many users exist.
3) Zenasis is offering to help library creation for your design
by using ZenCell Factory. It will help many SoC design team.
But on last stage of Sign-Off, library generation is painful.
4) A user needs to look at a dream, when using ZenTime. Improve
timing? Reduce power? Reduce number of Vth in cell library?
ZenTime will help designer to make dream true, but designer
has to have a clear mind that how you want use ZenTime, because
ZenCell's quality is depend on your criteria.
I am requesting Zenasis to reduce number of ZenCells that generate
from ZenTime.
- Yoshio Inoue of Renesas
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