( DAC 04 Item 40 ) --------------------------------------------- [ 02/09/05 ]
Subject: BindKey and Accelicon
IF YOU CAN'T BEAT THEM -- With all the challengers to Cadence Virtuoso, it
interesting to see two EDA companies taking the synergistic approach of
selling Virtuoso add-ons. BindKey is doing "yield" and "DFM" stuff and
Accelicon is a transistor-level floorplanner which feeds into Virtuoso.
BindKey RDC & RDF:
BindKey is a very interesting addition to Virtuoso editor consisting of
two tools: Rapid Design Clean (RDC) and Rapid Design Fix (RDF).
RDC is an online DRC check enforcer that runs in top of Virtuoso but can
read and adjust to all the 90 nm complex design rules. It has 3 modes:
Hint, Enforce, and Notify. Hint helps users to get a graphical "hint"
of the location with proper design rule. Enforce is like a magnet.
Notify tells the user where and how the errors occurs. This is a great
productivity improvement tool.
The race is on to see who is the best at fixing DRC errors and reduce
verification time. BindKey RDF started originally as a DRC fix tool,
equivalent with SiFix from Sagantec. It appears that from the time
Du Pont invested in them, they moved more toward DFM and recommended
rules fixes versus DRC cleanup. BindKey can deal with redundant vias,
spreading wires, move devices, poly end cap, line extension, most of
what PSM and OPC are doing after tapeout. To find fast all the DRC
errors they developed a fast DRC that looks impressive. Runs FLAT but
reports errors hierarchical and it is (claimed) 100x faster that
Calibre. This by-product may be a future tool for sale to compete
with the other DRC verification tools.
Cadence came up with a similar tool called DRD but it is not capable
(YET) to comply with complex rules at 90 and 65 nm. BindKey reads
Calibre DRC deck (claimed 100%). Nice addition to the Virtuoso editor
for low price.
Cadence has Optimize from Q-design. The tool will be part of VXL in
next revision and this is a partial polygon compactor. We have to wait
and see how Optimize measures up.
- Dan Clein, author of "CMOS IC Layout"
Accelicon AVP & ASI:
Accelicon had the most impressive new tool for analog layout transistor
level floorplaning presented at DAC 2004. The name is Analog Virtual
Prototyping (AVP) together with the Analog Silicon Implementation (ASI).
It is an analog solution for automated placement for devices. Imports
a schematic from Cadence, analyzes the critical path based on Spectre
or HSPICE simulator results, partitions the design and generates
automatically a floor plan with real size device. The user can modify
on the fly graphically:
- The floor plan, rearrange devices,
- Decide which devices to interlace,
- Can specify common centroid or symmetry,
- Change aspect ration of the box, etc.
Even though it does not own a router, the tool is parasitic aware; some
assumptions apply. It uses the Pcells available in the Cadence library.
Evaluates DC current numbers from analysis report with Spectre and
HSPICE. At the end, the user can export the result into Virtuoso and
call the VCP/VCAR, or another router to finish the job. All constraints
are exported to the router.
Constraints are back annotated to schematic so placement is maintained
even with ECOs for selected areas of devices. Constraints are defined
in AVP but can be viewed in schmatic and exported to ASCII text.
This tool is much more intuitive then NeoCell or anything else I have
seen yet. If you are in analog world, it is definitively worth looking
at Accelicon.
- Dan Clein, author of "CMOS IC Layout"
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