( DAC 03 Item 41 ) ----------------------------------------------- [ 01/20/04 ]

Subject: Silicon Metrics, Prolific, Z Circuit, Zenasis, UbiTech

A LITTLE SABOTAGE:  Magma acquired Silicon Metrics.  Circuit Semantics was
MIA and presumed dead this year.  Synopsys buying Numeritech has temporarily
screwed up Cadence, who relied on their tools for phase shifting and optical
proximity correction.  (Cadence is working on another partnership, but won't
talk about it yet.)


    I have used Magma/Silicon Metric's SiliconSmart CR, their library
    characterization tool.  It's a much, much better tool than the Avanti
    Master Tool Box we used before.  The thing I like the best about
    SiliconSmart CR is that it is very easy to port the characterization
    setup and configurations across different corners, or even different
    processes.  The biggest problem we have had is Silicon Metrics'
    inability to provide regular bug patches.  As a result, we tend to rely
    on ourselves to fix the bugs, since we don't have the luxury to wait
    till the next major release.
   
        - Jian Ding of Guidant Corporation
   
   
    Our eval compared Silicon Metrics SiliconSmart to our internal PERL-
    based characterization method.  We did take a cursory look at Circuit
    Semantics a while back, but this was not a head-to-head comparison.
   
    The SiliconSmart software is extremely configurable, almost to a fault. 
    We're running both standard cell and IO characterizations, with mixed
    voltages on inputs and outputs.
   
    The support from a small company has been exceptional, and they have
    really worked hard to make our adoption a success.  I am hoping none
    of this changes now that Silicon Metrics has been acquired by Magma!
   
    The product team is changing the capabilities of the SiliconSmart CR
    tool with respect to bidirectional ports, and our technical lead has
    been working with us to weather this transition. 
   
    Overall, it's a solid product from this customer's standpoint.
   
        - [ An Anon Engineer ]
   
   
    My company PolarFab is a state-side pure-play foundry.  First a little
    background about our usage of Magma/Silicon Metrics' SiliconSmart CR
    (I'll refer to the tool as CellRater, which was its old name).  We have
    relatively small libraries -- 110 cells per library or less -- and we
    have three main processes we use SiliconSmart CellRater on, 0.8, 0.5
    and 0.35um.  I drive SiliconSmart CellRater exclusively from the GUI
    and haven't put together any batch jobs yet.  Also, we use Spectre for
    our SPICE simulator.
   
    The CellRater/SiliconSmart CR Bad:
   
     1) CellRater is relatively slow.  Running on a 4-processor 750 MHz
        Sparc machine, it takes 2-3 days to characterize a 100 cell library
        for one corner.  To do the fast, slow and nominal corners for a 100
        cell library takes a little over a week.
   
     2) The license manager seems to get confused when there's more than a
        minimal amount of licenses activity.  To deal with this, I may have
        to terminate the session, exit the tool and then get back in.  This
        isn't too bad, more of nuisance.
   
    The CellRater/SiliconSmart CR Good:
   
     1) SiliconSmart does what it is supposed to do.  This allows us to
        create timing views for our standard cell libraries and develop
        SP&R flows for our customers' use.
   
     2) The "verify models" feature is great; every EDA operation needs a
        verification step.
   
     3) I'd have to say the customer support has been excellent.
   
    We are waiting for the next release of CellRater which will support the
    5.0 version of Spectre (due out end of January '04.)  This version of
    Spectre runs on Linux whereas previous versions did not.  Spectre 5.0
    also added a bunch of features that should speed up CellRater's
    characterization.  So, I am hoping for a 4X to 10X speed up by moving
    to this new version of CellRater, which supports Spectre 5.0, and
    moving over onto 3 GHz Linux boxes.
   
        - Kurt Kimber of PolarFab
   
   
    Library Generation and Characterization

    Silicon Metrics sells software to characterize libraries. They told me
    their primary competition is still internal tools. They support the new
    Synopsys SPDM model with signal integrity information and also new
    Cadence constructs that provide improved driver models for victim nets.
    Until recently there was no standard way to express glitch sensitivity
    and glitch information.

    Library Technology Inc. sell library characterization tools, but also
    has a tool to optimize transistor sizing for delay, power, clock skew,
    etc. This sounds like an "analog synthesis" tool being used for digital
    libraries.

    Prolific sells software that generates the layouts for libraries. They
    now have both generators (slow to set up, fast to generate, fair density)
    and synthesis (transistor place & route and compaction) (fast to set up,
    slow to run, high density). They also sell Protiming, which sizes cells
    to optimize timing. It ties to Primetime and they claim they can get
    1%-2% improvement using existing cells (what does that say about timing
    optimization?) and they've seen 6.5% to 15% timing improvement by
    creating new cells at custom drive strengths. They also claim that Design
    Compiler uses maybe 5 drive strengths of any given cell no matter how
    many different drive strengths are in your library.

    Zenasis sells a tool that does transistor level optimization of your
    design. The input is a Verilog netlist of your design, LEF/DEF, a
    Synopsys library and SPICE description of your cell library. The tool
    creates new standard cells that combine cells in the critical paths.
    The output is SPICE description of these new cells, which you can create
    using Cadabra. They claim a 10%-17% increase in speed using their 
    technology and say Agilent is a customer. They will also sell services
    to create the new cells.

    Z Circuit Automation sells a unique tool that compares libraries or cells
    within libraries. This sounds difficult to sell but I've worked with at
    least 20 libraries in my career and every single one of them has had
    bugs. The tool works from a .lib and can compare different revs of the
    same library as well as point out the best load/slew ranges for a cell
    or a library.

    Legend Design Automation sells a tool to characterize memories. They
    emphasized the need to characterize a memory for your specific system,
    and said they do power characterization as well.

        - John Weiland of Intrinsix


    Library Technologies

    Library Technologies provides a cell characterization tool that supports
    standard cells and I/O's at no extra cost. The tool supports the latest
    Liberty file formats for timing, power, and noise. For timing, both table
    lookup and scalable polynomial delay models (SPDM) are supported. It also
    supports state dependent timing, power, and leakage power. The tool does
    not do a functional extraction of the cell and thus requires a small
    descriptor file for each function. From this functional description, the
    tool automatically creates an exhaustive Spice simulation file and
    Verilog test bench. Many user control options are provided for things
    such as setup and hold time measurement method, noise model generation,
    and others. Both Verilog and VHDL models are supported.

        - [ An Anon Engineer ]


    We used Z Circuit's services for library re-characterization to a
    different operating point, to basically reduce some of the over 
    margining that normally happens during design.  Our experience was very
    smooth and pleasant. No surprises. They provided us with detailed
    comparison reports for each of the timing arcs, for each of the cells
    between the two operating points, in a consolidated form to

      1. Validate the correctness of the re-characterization, i.e. make
         sure that everything that's unexpected or outside of expected
         range is explained for completely.
      2. Give us a good feel as to what we can expect in terms of the
         performance of the library

    The Z Circuit library analyzer in general is very versatile and powerful
    and can be used to compare libraries to understand their impact on a
    given design.  Edmond and Fred (the two key people at Z-circuit that I
    had the opportunity to work with) are very knowledgeable, and we used
    them as sounding boards for some of the issues we had to deal with
    during our design. They were very helpful and provided valuable feedback.

        - [ An Anon Engineer ]


    I think I saw the Z Circuit Library Analyzer demo here.  We haven't used
    Library Analyzer in any real way.  It looks interesting.  I don't know
    of anything else that does what it does though there are likely some out
    there.  The bottom line is that no one has found it interesting enough to
    take project time to look at it.  I suppose that says something...

    The net is that I think the tool would be useful.  I'd like to look at
    it.  And, I can't really tell you much more than that.

    I've done some work in the past around looking at gobs of data (rspf
    comparison plots).  From what I saw from Z-circuit, they present the
    data in a meaningful way.

    There were two uses that we considered for Library Analyzer.  First,
    comparing library versions to each other.  You know, you're coming up
    to tape-out and your ASIC vendor says you need to upgrade your library.
    You ask what's changed and they can't really tell you.  The second use
    was more in line with how Z Circuit is marketing their tool: analyzing
    libs to look for strengths or weaknesses.

        - [ An Anon Engineer ]


    I usually do not look at backend tools but the coolest new tool I saw was
    from Z Circuit Automation which had a tool to compare two versions of a
    vendor library.  I am not sure which is worse that this was the neatest
    new tool or the fact that we really wish we had a tool to do this.
   
        - Steven Jorgensen of Hewlett-Packard
   
   
    The company that struck me as the interesting new vendor is Stone Pillar
    Technologies and their Silicon Insight Software.  They provide linkage
    from the fab process, through the transistor level design optimization
    business process flow, to the IC design environment.  Their data
    structures spans process, device, modeling and test structures.
   
        - Peter Hopper of National Semiconductor
    

    Mentor Calibre does optical proximity correction and phase shifting.

    UbiTech sells tools to add metal fill for Chemical-Mechanical Polishing
    (CMP), which requires that every area of the chip have roughly the same
    percentage of metal coverage. They do the setup for xCalibre for easy
    extraction setup. Their tool will avoid critical nets if they are
    identified.

        - John Weiland of Intrinsix


    I tried the UbiTech product.  It has some benefit in reducing loading
    on critical nets, but not enough to justify the price for our
    applications.

        - Louis Morales of Innotech Systems



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