( DAC 03 Item 39 ) ----------------------------------------------- [ 01/20/04 ]
Subject: NeoLinear, Antrim, Ciranova, Barcelona, ADA, Xpedion
CADENCE IS CIRCLING: Cadence absorbs the remnants of Antrim and then cuts
an OEM deal with NeoLinear to resell some of their tools in the U.S. market.
A number industry watchers see this as a trial living together before Cadence
actually buys NeoLinear. On the analog synthesis front, Ciranova was the new
kid that was noticed at this year's DAC. I'm not saying that as a technical
evaluation; but from the conversations I heard from venture capitalists at
a bar while at DAC. On the technical front, I think most analog designers
tend to shun analog synthesis altogether. That is, it's still an evangelical
sales problem because most analog designers I've known see analog circuit
design as more of a un-automatable black art. But who am I to disagree with
venture capitalists? They are the people who brought us the Internet bubble
you know! :)
We do not use these tools.
I believe that Barcelona has a great potential as the concept is right
and the industry needs a tool like they have.
- Yuval Itkin of Metalink Ltd.
Barcelona belongs to the analog IP market. Antrim is gone, or was asset
purchased by Cadence (which is almost the same as gone). Replacing
Antrim is Ciranova, with the same simulation based optimization
methodology as Neolinear and ADA. Ciranova needs to exceute their tool
development, and they need to do it promptly, before the Neolinear and
ADA take over the whole market.
Neolinear seems to have finally come around with the result exploration,
which is one of the most important issues for practical analog designs.
It would be nice to see how Neolinear and ADA play out in the next 6
months, by which time we will start to evaluate one of them.
- Weikai Sun of Volterra
There was almost universal agreement among competitors that the Antrim
Design netlist sizing tool that Cadence bought, while fine for modest
size circuits, runs out of steam sooner than most of the competitors
when dealing with big circuits, lots of environmental corners, or lots
of constraints that you are trying to meet. Interestingly a number of
them also agreed that Antrim is probably the best at handling the huge
amounts of data you generate when you optimize a netlist. If there is a
way to hook other optimization tools into this then that will again
help keep Cadence as the central framework.
Mentor has its own set of analog tools that they claim are competitive
with Agilent ADS and more capable than Cadence.
Barcelona Design probably comes closest to the dream of spec in, GDSII
out, but does it on a very restricted set of design types. They have
fixed netlists for op-amps, PLLs, and ADCs (6-10 bits). You put in your
requirements, and it sizes the netlist and produces the layout.
Generators for DACs and multiphase PLLs are coming. They said they use
a mathematical approach to sizing versus random SPICE runs, which I guess
you can do if you have only a few netlists you need to work on. Their
engines work for TSMC 0.18, 0.13 and 0.09 and UMC 0.13HS. They said they
did 35 tapeouts last year and all met spec.
Neolinear sells tools that not only size your netlist based on various
constraints you provide but will also optimize a layout. I think this
layout optimization capability is unique and Cadence actively supports
this aspect of the tool but not the netlist sizing portion that overlaps
their Antrim Design purchase.
Analog Design Automation sells a tool which sizes netlists. They say
they can optimize up to 200 variables (they claim Antrim/Cadence can
only do 30), up to 60 corners and up to 30-40 objectives. One
interesting thing about their tool is that it provides multiple
results, each optimized in some way (maximum speed, minimum power, etc.)
Xpedion sells analog design tools that they claim are faster and have
more capacity than Agilent and are better integrated into Cadence. They
are particularly proud of their fast envelope transient simulation and
say they converge better than Agilent.
Anasift sells software to automate op amp design. The input is a SPICE
netlist, SPICE model and your requirements and the output is a sized
netlist. They hook into Cadence's tools.
- John Weiland of Intrinsix
NeoCell - Neolinear is moving in the same direction as before but they
can cope with one axis of symmetry only and still uses proprietary module
generators instead of PCELL. The numbers of constraints that have to be
setup is 1000+, make sense in repeatable architectures that are the bread
an butter for many architectures. Now the tool has an area based placer
rather than a row based before, and constraints can be entered now
through a built template that can be reused. Good steps forward for an
integration with Virtuoso but not there yet.
- Dan Clein of PMC-Sierra
Let me first off state that my basis for comparison of NeoCell is
Virtuoso and HP/Agilent's old, internal tool. In my dealings with
NeoCell, I worked with them to do an evaluation of an amplifier I had
previously design and laid-out by hand. For the most part, they
performed the layout in NeoCell, and I did the comparison. The IC that
I planned on using NeoCell to lay out changed scope prior to getting to
use it for a "real" project, and NeoCell was not included in the PDK the
design was eventually done in.
NeoCell was very good for creating objects that required a good amount
of symmetry, or matching (diff. pairs, current mirrors). Its ability to
perform symmetrical object moves (picking one object and having its
partner move symmetrically with it) was really nice while trying out
placements of cells. One catch with the symmetrical layout, which they
tell me is being worked on, is that you can't specify that two nets
should have equal loads on them. I also liked the DRC fix function.
The tool would make the necessary corrections to fix a DRC violation.
This was the main basis for my evaluation since it didn't get much
farther than this.
The was an improvement over Virtuoso-XL just in keeping track of the
relationships between components, among other things. There is a bit of
overhead in setting everything up in NeoCell, but it is worth the
effort. And I think it is probably worth doing for designs without the
tool, since it would help straighten things out in one's own head. I
guess I'm saying it is not a waste of time and effort.
I remember having trouble getting the pins the way I wanted them based
on the symmetry rules that had been set up, and issues changing the flow
of the signal -- a differential pair oriented one way flowing into a
folded-cascode oriented another way. I didn't get far enough to see how
big a problem this would be.
I definitely feel there is benefit to using NeoCell, and can tell you
that I will push for getting it integrated into my PDK once we have
settled on the process we plan to use. Here is a quick summary:
Strengths:
- great for designs that require matching (diff. pairs, current
mirrors).
- auto router.
- keeps track of component relationships for you.
- DRC fixer (automatically fixes DRC errors).
- excellent customer support.
- works with Cadence environment (with additional setup).
Weaknesses:
- not being able to specify "net" symmetry.
- reasonable amount of overhead to get things set up.
- menus are a bit confusing (no more than other tools).
Overall: I think it would be worth using.
Since my evaluation was quite some time ago, this is about what I can
remember. I plan to get involved with NeoLinear again some time mid-
next-year to get things rolling in terms of using NeoCell.
- Mark Maloney of Agilent
We basically use Cadence Pcells, Virtuoso-XL and VCR/CCAR (together
Cadence calls it their ACPD flow) for basic device & block level
routing. We have been using NeoLinear's NeoCell for two years, mainly
in pure analog designs. We have gone thru many of NeoCell's releases
from R3.0 till the latest R3.3.3.
The good stuff:
- can optimize MOS, resistors, and capacitors thru its Module
Generator (ModGen), to create PIMA, PMRA and PICA devices, which is
to produce inter-digitized, arrayed, .. optimized structures.
- provides 12 most-commonly used analog constraints (like symmetry,
matching, ..), and use them throughout auto placement and routing.
- good integration with Cadence VXL, and can handle pcells as well.
- after user can master the tools pretty well, it does save time in
layout interations.
- produces reasonable results in reasonable time.
The bad stuff:
- no comprehensive ECO flow.
- lack of flexibility, for instance, allows user to add blockage on
some sensitive devices or areas for no-routing, add substrate or
well taps.
- cannot handle complicated MOS, resistor device structures.
- cannot handle optimizations for bipolar devices.
Also runtime performance can be further improved, and not available on
Linux yet.
- Jason Chen of National Semiconductor
It's been a while since I looked at NeoCell, and I am no longer in the
ASIC design group. I thought NeoCell was a good tool and I would have
been glad to have it for design work. I have used Virtuoso but not /VXL
or any other NeoCell equivalent. I have used the Agilent MDS optimizer
for microwave frequency work. I thought NeoCell was easy to setup and
use. It is useful not only for optimizing circuit parameters, but it is
also useful for quickly evaluating different circuit topologies.
Strengths: Quick and easy setup plus a good user interface.
Weaknesses: I did not have any complaints about NeoCell.
- Stephen Fahley of Boeing
We had a protracted evaluation of NeoLinear's NeoCircuit, due to legal,
financial, and project complications. We eventually decided to pick it
up based on the job it did on three demo circuits -- it did do an
impressive job of improving these. The fact of the matter was we were
able to spend money on new tools, but not new people, and we needed
tools to improve the productivity of the people we had. NeoCircuit
looked to be the ideal solution.
We did have a problem with NeoCircuit though, even if it was of our
making. We use an extensive suite of schematic pCells (the same pCell
is used for schematic and layout, so all parasitic effects are built
in). Unfortunately, these pCells lacked some of the standard Cadence
functionality that NeoCircuit requires. Such is the nature of the game
that I have never got around to re-implementing the pCells to support
NeoCircuit, so we have never actually used it in anger (yet).
I have looked at, but not evaluated, the competition -- ChipMD, and one
other new guy that was at DAC. I wasn't impressed. NeoCircuit is
tightly integrated with Cadence, which is a joy if you have a full
Cadence flow. It also works extremely well with NeoCell (which is
distributed by Cadence). It does require a different way of working
(you should parameterize as much of your circuit as possible), and
promises to do a great job of re-targeting technologies (which is
something we also looked at it for).
NeoLinear also has a parameterized library of analog cells which could
be useful to an understaffed group, if they can afford the cost of
NeoCircuit in the first place. From an analog standpoint, you simply
need to pick a topology, a technology, and a set of target performance
specs and NeoCircuit does the rest. If you have a lot of legacy
circuits, you should allocate time to go back and prep them for
NeoCircuit -- I wish we had done that. You'll then be able to re-use
them quickly.
- Steve Avery of Cisco Systems
My experience is one of evaluations only, I have not used the product in
an actual design. My recent background is in RF circuits using Agilent
ADS & MDS.
I have reviewed NeoCircuit, NeoCircuit RF, and some of the tools
NeoLinear is working on for RF applications, e.g. NeoCell RF, Pebble
Beach, Gulf Stream, and Icarus. I think the major strengths are its
ability to do large circuit optimizations. Cadence and Mentor have some
of this capability, but they get bogged down when trying to do large
circuits with many parameters to be optimized. NeoCircuit does this
optimization by using many licenses, on many machines. Purchasing the
many Cadence licenses that would allow efficient use of the optimizer
could be expensive, however in a large organization, they may be
available anyway.
- Rodney Bonebright of Boeing
I have seen the NeoCircuit demo, and gone to a half-day workshop on
their "RAD" flow. I have also seen a demo of ADA's tools. Both ADA and
NeoLinear have intelligent ways for you to set up constraints for device
sizing of an analog circuit topology. Since I haven't run the two tools
on a test design, I cannot say whether one or the other does a better
job converging on an optimized solution. This would be an important
thing to do if you were choosing one of the two tools. If one tool
consistently found a good solution in fewer iterations (and therefore a
shorter time) that would be strongly in its favor.
ADA has a better way of looking at the various solutions generated by
the circuit sizer. I think they package it as a separate tool and call
it IP explorer. That data viewer is their distinction. NeoLinear is
trying to introduce a similar viewer, but it is not as good.
NeoLinear's advantage is a closer relationship with Cadence and a bigger
installed user base. On balance, I think that if choosing between the
two, I would want to go with the one that consistently converged on
solutions faster.
I like the idea of having a circuit sizing tool, but at a cost of
roughly $80,000 dollars a year per seat, it is not easy to justify. If
you often port similar designs from technology to technology, I believe
having one of these tools would be an asset.
- Mike Maliepaard of Gennum Corp.
|
|
