( DAC 03 Item 38 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Mentor Calibre & Calibre-XRC & Eldo
HAPPY MENTOR: Don't have the recent Dataquest numbers, but my gut tells me
when they come out that Mentor Calibre will easily have a 60%+ share of the
LVS/DRC market. Technologically, Cadence Dracula/Diva/Assura is the laughing
stock here. Avant Hercules is a respectable 2nd place player that had the
advantage of being native to Milkyway -- hence faster run times -- but Mentor
has announced that Calibre will run in Milkyway, so there goes that edge for
Hercules. The long standing advantage that Calibre has over Hercules is that
it's *not* native to the Avanti toolset. That is, shouldn't your Design Rule
Checking come from someone other than your P&R vendor? Otherwise how can you
have a genuine check going on? :)
Eldo is:
- As user frieldly as HSPICE but faster
- As powerfull (for behavioral description) as Spectre but much more
easy to use in batch mode (for cell charaterisation & lib development
for instance)
- Has some extension for accelerate MOS simulation ("like Nanosim") but
this module is still fragile and doesn't work very well -- needs more
tuning I guess
- Has some RF extension that surprisingly work fast and very well for a
new product.
Eldo's integration in Cadence Analog Artist is very good; sometimes even
better than Spectre... but there is still room for improvement.
The waveform display is getting old now, and is not very efficient (but
at the same low standard as the Cadence one). Although it provides a
lot of analog features, it is not very user friendly.
The first version of the new engine from Mentor (EZwave) shows that
Mentor learned a lot, and will cover all the needs for both mixed signal
and analog/RF users.
AdvanceMS is starting to be deployed in ST with big success for telecom,
STB or disk drive. VHDL-AMS is our preferred language (mainly for
historical reasons) for ST behavior AMS model developers. Verilog-A
implementation in ADvanceMs is slower than the Cadence one, but Mentor
is working hard on that issue. It allows the designer to mix SPICE or
behavioral descriptions, and it manages RF envelope simulation and
MachTA acceleration.
Early Cadence AMS users aren't happy at all. Additionally, we have
trouble defining a correct structure to manage the model in Cadence AMS.
It doesn't understand exact Spectre models. Thanks Cadence for the
extra work to develop wrappers in Verlilog-A for my standard Spectre
models.
- Jean-Paul Morin of STmicroelectronics
We are using the Mentor's Eldo simulator and we are happy with the tool.
We are also using Synopsys PrimeTime as a timing checker (but recently we
discovered that the tool does NOT support clock gating correctly as it
uses a global setup/hold value for all the gators in the design which is
wrong).
- Yuval Itkin of Metalink Ltd.
In terms of GDSII verification, Calibre is still the fastest based on
people comments, but.... Hercules is improving the extraction and Assura
is working hard now to improve runtime. I am sure that in the next 2-3
years each one of them will improve in another domain. For now debugging
is easy with Assura, but runtime is better in Calibre. Interesting
enough Synopsys did not bring a demo of Hercules for DAC???
- Dan Clein of PMC-Sierra
From my experience Mentor wins the LVS race hands down. It's ability to
handle big chips with large embedded memories is very impressive. The
runtime for LVS on one of our chips (~65 million transistors) is about
three hours. In terms of DRC performance, we again choose Calibre for
it's performance, ease of use, and it's intuitive DRC coding style.
Regarding Hercules and Assura, my momma always said "if you can't say
anything good, keep you darn mouth shut!". ;-)
- Charles Schmitz of Motorola
My company has bent over backwards to adopt Assura as the official
physical verification tool suite over the past couple of years, but the
users are still 'voting with their pulldown' for Calibre overwhelmingly.
There are a couple of groups who have a pretty slick, very elaborate
infrastructure built up around Hercules which they are hestitant to
abandon, but almost everyone else is in love with Calibre. The attempt
to move to Assura, from an 'official tool' perspective, was two pronged.
One was financial, in that removing Calibre would greatly reduce
Mentor's presence here, almost to the point at which they could be
dropped entirely (bean counter nirvana!). The other prong of the drive
to move to Assura came from some of the groups that focus on analog
designs. Those guys like the relative complexity/flexibility of
Assura device definitions and such, and are willing to bite the bullet
with respect to run time and tool maturity.
I think that, though it's taken quite a while, if we can just get the
Calibre/StarRCXT flow working smoothly, Assura will be dead at Motorola,
Hercules usage will continue to wane, and the natural order of things
will have been restored.
I personally have been on the front lines of attempting to sway our
company away from Assura. Suffice to say that Calibre is by far the
faster, more mature,and more user friendly solution. Hercules was
cutting edge back in the ISS days, but Calibre is "hierarchical lvs/drc
done right". Assura is very poor at handling designs with a lot of
hierarchy, especially if there isn't rigid correspondence between the
hierarchical construction of the GDS and SPICE files.
- [ An Anon Engineer ]
I am getting increasingly frustrated with Dracula, especially knowing the
awesome capability of the Calibre. We will probably migrate over to
Calibre sometime in the near future.
- Nicco Bhabu of Chip Express
I've used both Assura and Calibre, but not on the same designs, so it
will be hard for me to do an apples to apples comparison. However,
these are the results I've found for the two tools.
I've used Assura much longer than Calibre, but there's no doubt Calibre
is a superior tool in terms of performance and ease of use.
Calibre is very fast. It has easily handled all the designs we've
thrown at it. The largest size GDS we've verified with it was 410
MBytes. This was in our 0.13u technology. One design I placed and
routed in that technology was just over 250 MB and DRC ran in
5234seconds on a 28-processor Sun Ultra Enterprise 6500.
We have not used Assura for a 0.13u design, only for 0.25u designs,
because Cadence has not demonstrated that Assura can scale to designs of
this size and complexity.
The graphical error viewer that interfaces with Cadence Virtuoso is more
elegant and easier to use than Cadence's own Assura viewer, although
Assura has more configurability in terms of the way error layers can be
displayed.
The rule syntax in Calibre is straightforward to read and write compared
to the Skill-like syntax used in Assura, and I wrote the Assura DRC and
LVS decks for our operation.
In LVS, the extracted layout netlist is in a Spice format, so it is easy
to read and understand. By default, Assura outputs the layout netlist
to a binary, proprietary format that you need to run a tranlator on to
read. In terms of resources used, Calibre requires about an order of
magnitude less disk space than Assura for designs of comparable size.
The comparison utility for Assura LVS is extremely slow compared to the
one for Calibre LVS. I'd say the Calibre comparator is at least 5X
faster. Assura does have the advantage that it can run directly off a
Cadence DFII database if it is desired. Calibre runs off GDSII and
SPICE only.
Assura reads Verilog directly, while Calibre only reads SPICE. Mentor
provides a Verilog to spice translator that works well, though.
- [ An Anon Engineer ]
I have been working closely with Cadence and Mentor since the early days
days of their tools (late 80's for Cadence and early 90's for Mentor).
As much as I am harsh on Mentor to get their tools right, I found the
Mentor tools under Cadence environment or as stand alone outperform that
of Cadence for telecom and networking application (high content of
analog/ms). In addition, I can say I am much satisfied with getting
response from Mentor than with Cadence. It was much easier to influence
the development of Mentor tools to incorporate in-house niche
capabilities into Mentor tools (e.g. transient noise, optimization,
generic models integration) than doing the same with Cadence. Mentor
support is far better than any other EDA company. Their main problem is
that they fall short of how to sell their products in North America or
how to capitalize on their good customer relations."
- Farag Fattouh of Intel
Few comments about RC extraction:
1. For RC extraction from LEF/DEF, we use Star-RCXT.
2. For RC extraction from GDS, we purchased last year Calibre-XRC,
which replaces our old Arcadia.
3. We have 2 working modes with Calibre-XRC:
- For digital blocks: RC extraction in gate level, were the
output is DSPF file that can be read by PrimeTime. We use
this flow to extract full blocks, or selected nets that passed
ECO in the layout.
- For analog blocks: RC extraction in transistor level, were the
output are SPICE files, flat or hierarchical.
Hope this helps in your survey.
- Eyal Landesberg of Zoran Israel
We evaled Assura 3.0, Calibre XRC, and Star RC-XT last fall. We were
pleased overall with the Assura extraction engine (despite certain
issues/quirks that most other people wouldn't tolerate), but lack of
support for DSPF or macro/black-box cell type of flows prompted us to
take a look at other solutions. BTW, we are using Simplex for LEF/DEF
DSPF (cell-level) extraction, with no plans to move to Calibre XRC in
the immediate future. In that evaluation, we found found XRC to excel
in the areas we were focusing on. Performance was in-line with Assura
(both better than Star RCXT), and we determined that migration issues
from Assura to Calibre would be small enough to warrant moving to XRC.
The evaluation ended early Q1 of this year... since then we have been
waiting for management to strike a deal for the purchase of Calibre XRC.
We've been working on integrating it, but haven't really been using it
much on actual designs, so I don't know if I can really provide
meaningful comments on strengths or weaknesses yet. I'll give is a
shot, though:
Calibre XRC Strengths:
- Part of the Calibre hierarchical engine, which to me implies good
code development practices and a large customer base
- Good black-box LVS/extraction techniques
- Like xCalibre, user-customized structures can be used for generating
techfiles
- Multi-threading/LSF capabilities are impressive, but I haven't
really had the chance to characterize them yet
Calibre XRC Weakness:
- We found a problem with capacity on a large GDSII block needing DSPF
extraction (Mentor said it was a bug they would fix). How frequently
this type of issue will arise is a major concern.
- It is expensive for us, as we are not a customer of Mentor at this
time (that's why we are sticking with Simplex/Cadence for DSPF on
logic blocks)
- It is going to require some enhancements to be able to achieve the
same functionality with Simplex analysis tools that you get with
the Assura extracted view
Having recently benchmarked the Calibre DRC/OPC tools, I'm ready to move
to Calibre for all physical verification.
- Jarrod Brooks of Cypress Semiconductor
Talking about extraction, I would say that only working experience I
have is with Mentor Xcalibre or XRC. We looked at other rival tools
like StarRC and one from Synopsys but that was a long time ago, and I am
sure those tools are also improved a lot since we looked them last.
Let me give you a little bit background about out culture here. We are
mostly a custom design house. Very recently we are also playing around
with ASIC stuff. Our design engineers are quite experienced people and
are very rigid in terms of their choice about EDA tools. They still are
using some of the waveform viewers like GSI [from Metasoftware + Avanti]
which are out of maintenance for years but they love the features GSI
has and won't even think about another tool unless GSI breaks down all
of sudden one day.
People were never happy with the difficulties in using extraction tools.
They would rather measure the parasitics by hand for very critical
circuits. They wanted features like selected net extraction, RC
extraction in a very convenient and easy to use manner.
We started with xCalibre-PX and boy, the only thing we got from the tool
was lumped C extraction. We were never satisfied with the performance
of the tool especially with RC extraction.
Then came XcalibreH. This tool had some more advance features like ASIC
kind of interconnect extraction, selected net extraction, etc. But
the capacity of the tool was always an issue. There were quite a lot
constraints from layout point of view required by XcalibreH when it came
to ASIC kind of interconnect extraction.
One of our reasons for sticking with Mentor extraction tools was our
physical verification suite that was based upon Mentor Calibre DRC and
LVS. Also we were quite satisfied with Mentor technical support as
compared to some of their rivals.
We started looking at Calibre xRC in the beginning of 2003. We have
successfully adapted this tool in following areas:
1) Luped C extraction [SPICE]
2) Distributed RC or RCC extraction [SPICE]
3) Selected net extraction with C or RC or RCC [SPICE]
4) ASIC interconnect extraction for static timing analysys [DSPF]
5) Selected net interconnect extraction.
We are looking at hierarchical extraction features at this point and
also some graphical parasitic result viewer [RVE].
But we have spent lot of effort in past to adapt Calibre DRC and LVS and
now Calibre xRC in our design flow. We have worked with Mentor like
crazy to get bug fixes and the new features we wanted and for our better
understanding of the tool. Before using extraction tools we were also
familiar with Calibre LVS which is integeral part of Calibre xRC. For
any new customer it may take a while before they really start liking the
tool. We had to convince our design community a lot when we migrated
from Hercules to Calibre verification tools few years back. But slowly
we were able to overcome the initial difficulties we faced.
We still keep the Mentor support line busy with new issues we encounter
and the good news is the Mentor releases a patch or new release almost
every month that way we don't have to wait a lot for bug fixes.
Here are the good points of xRC as it stands in our design road map at
this point:
1) Large capacity to extract parasitics at least as compared
to XcalibreH or xCalibre-PX.
2) Easy of use after we have done lot of scripting to make
this tool user friendly.
3) Good customer support.
4) Reasonable accuracy. We benchmarked calibre xRC results
against reputated field solver.
5) Fits our needs and design flow.
6) Good customer support. Experienced AE's to help you through.
7) Ease of writing rule decks.
And finally some weak points:
1) We don't know how it stands against rivals. Our knowledge very
much limited to Mentor extraction tools.
2) Often have issues when handling hierarchy.
3) IF you don't use Calibre physical verification suite like Calibre
LVS, it may be a real pain to use the tool for first time users.
- Sandeep Saini of Lattice Semiconductor
About Calibre xRC:
- Calibre xRC is 25 times faster than xCalibre. However, xCalibre
speed was poor, especially when extracting resistance and
capacitance.
- We use xRC for custom layout. I still do not believe it is fast
enough to do full-chip extraction, but it is quite capable of doing a
large custom block such as an embedded memory or an ALU. It is also
accurate. My definition of "fast enough" is completion in less than
24 hours run time on a high-end server.
- Converting from xCalibre to Calibre xrc was relatively painless.
- In my previous company we used StarRC to do full-chip extraction.
StarRC had a big speed advantage over xCalibre, but sacrificed some
accuracy -- but that was several releases back.) We used xCalibre
for cell and macro-level extraction.
- In my opinion, Mentor has the best AEs in the industry, which helps
make up for the poor quality of their documentation. They also have
a stable set of programmers -- because they are not in Silicon
Valley -- which leads to software that always evolves into something
better as time progresses, rather than abandoned software and
wrenching change into the unknown, which is the hallmark of the
Silicon Valley EDA industry.
The other products, Calibre DRC/LVS, especially hierarchically LVS, are
unbelievably fast and reliable. I think Mentor now have about 2/3 world
market share because nobody else can come close to Calibre's
performance. I would recommend these products to anyone doing VLSI IC
design.
- Bill Walker of Fujitsu
I am a Mentor Calibre user. I have used Hercules a few years back, and
my opinions on Calibre are mostly in comparison with Hercules.
Both Calibre and Hercules are comparable. Some of the differences are:
1. Calibre is generally faster across design styles, more powerful and
is more user friendly to code (in SVRF).
2. Calibre is particularly good at edge manipulations as oppose to
polygon manipulations.
3. Calibre is simpler to code for in LVS aplications.
4. Calibre does not do a good job of reporting LVS errors related to
ports of a cell.
5. Calibre is great at running on multiple CPUs within a single machine.
6. Hercules is better at running on multiple machines.
Dracula is outdated software.
- Fernando Aires of AMD
I have been using Mentor's Calibre for 3 years now. I was a hard core
user of Cadence Dracula for verification before running Calibre. I also
have experience using Hercules.
Calibre has the "RVE" or results viewer that plugs right into the
Cadence layout tools. And with the added feature of hierarchical
checking, things worked like a breeze.
When we looked at LVS/DRC verification tools we looked at them all. We
were looking for a tool that would be easy to install, easy to maintain,
easy to interpret provide the best verification possible. With mask set
costs these days, we wanted to be sure our data was correct. At the
time we were looking for a verification tool, Cadence did not have a
hierarchical LVS/DRC tool that could be compared to Calibre. And Avant
Hercules seemed to have numerous problems. My experience with Hercules
was that it was very difficult to understand the output. For our test
case, we ran Hercules and Calibre on the same data and found that
Calibre actually found a error that Hercules failed to find.
I am a changed person since using Calibre. I maintain one rule flow for
LVS and one flow for DRC's. So for me Calibre is very low maintenance.
It was very easy to get it up and running and the Mentor support is the
best I have ever experienced -- and I have been doing layout for 23
years. If I have any problems I just call Mentor Support and they get
back to me with in 30 minutes. We currently switched to running Calibre
on Linux and boy does it run fast!
I do not switch to the new releases every time they roll one
out. But then I don't know many brave souls that do run every new
release of software before testing it out.
So in summary, I do love this tool. I have not had any problems with
Calibre and I am very happy with the Mentor support group. We at
Pixelworks made a very good choice.
- Jeff Bates of Pixelworks
I have been supporting the Calibre tool for a while. I am not
directly using it but rather preparing the design environment so that
designers can use this tool as easily as possible. Thus I am able to
collect feedback from many design groups in our company. Calibre is
still showing reasonably good performances for current processes (90nm).
Nevertheless DRC, LVS times are increasing. Due to circuit size and
complexity increases, it's questionable whether Calibre performance
will still be OK for the next generation(s).
Calibre tool quality is acceptable, even if from time to time we
experience some regressions.
- Jean-Claude Marin of STmicroelectronics
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