( DAC 03 Item 29 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Tera Systems TeraForm, InTime Time Builder
TOUGH SELL: Taking the floorplanning paradgm one step further into what
Gary Smith of Dataquest calls "Silicon Virtual Protyping", Tera Systems
and InTime make what I call "estimators". Basically these tools take your
RTL and estimate what its best floorplan, power, and gate count will be.
Tera Systems has been around longer and their TeraForm tool even works
with blocks amazingly close to DesignWare parts. InTime is the relative
newcomer here. The problem that both companies face is that lots of
engineers like to do a quick & dirty floorplan & synthesis run to get
ballpark numbers for how their chip will work out. The upside to these
estimators is that they can catch all sorts of RTL coding errors that
mess up downstream synthesis and P&R. They also do it with a MUCH faster
runtime than the quick & dirty I'll-do-it-myself approach.
InTime Software sells an RTL timing tool. Like its competitors, they pre-
characterize a library of large blocks for your particular synthesis and
place and route tools. Unlike their competitors they will characterize a
new foundry for free or will give you the characterization scripts for
free. They do RTL floorplanning that generates LEF and can feed Cadence
SoC Encounter. They have their own timing tool.
- John Weiland of Intrinsix
Another interesting tool that I saw that somewhat fits into this category
is Time Director from InTime. It goes one step further in that it
assigns timing to the result of the "fast synthesis" step (claims of 20%
accuracy to industry synthesis tools). Critical paths can be identified
via graphical cross checking to the source RTL although the example they
were showing out on the floor was rather simple (a long "if-then-else-if"
chain for which a "case" statement was recommended).
- Jeff Waite of Chip Express
I will give you as honest of feedback as I can. First of all my only
exposure to Icinergy was ~2 years ago at EDA Front to Back (I think, but
it may have been DAC). At that time I was not very impressed with the
tool. That being said, I was not looking to invest in a tool which I
would call a nicety tool (i.e. not a necessity tool). Money was pretty
tight then as it has been for the past couple years, so you can see my
mindset. My exposure to Intime is also very dated. I saw them at DAC
2001. And then through a mutual friends at my company and Intime that I
was asked to re-evaluate the tool. So we coordinated an onsite visit
around Nov 2001. I was given a presentation and demo of the tool. I
thought InTime was on the right path but it was still very far behind
in capabilities and stability when compared to Tera Systems Teraform.
That is my honest opinion. Now for the disclaimer. I indirectly work for
LSI Logic Corp. LSI Logic has standardized on Teraform RTL as the golden
tool to perform a number of architecture & RTL rule checking as a
signoff requirement. The evaluation came down to two companies. The one
who could deliver a certain set of capabilities by a certain date would
be chosen as the golden tool. Tera Systems was the winner. We have been
effective at using TeraForm to uncover issues with customers designs
early in the design process to save us grief on the physical design
side. However we have not used the virtual prototyping software from
Tera Systems (TeraForm VP). I hope this helps.
- [ An Anon Engineer ]
Where TeraForm is today in our flow is the result of a very cooperative
effort between our team and Tera's technical staff and R&D. It's helped
us cut large loop iteration PD problems that should have been fixed in
RTL or floorplanning. Over past 18 months TeraForm has added Linux
support, revamped library characterization and creation, and additional
synthesis and physical partitioning options.
I like it.
- Darell Whitaker of IBM Microelectronics
I was very involved with the evaluation, selection, and continual drive
for improvements of TeraForm up until I got pulled into RapidChip
development and presales full-time a year ago. Here's my take on
TeraForm overall.
From a silicon vendor perspective ...
No customer likes to be told how poorly they have coded their RTL even
if it is true. I'll go so far as to say RTL is poorly coded 75% of the
time. You surely see this in your role. Hardly anybody codes for the
physical effects (local MUXing for example) and has a rough floorplan in
mind before coding.
The FPGA guys haven't even encouraged floorplanning up until recently so
customers haven't done it. I'll say that most unique designs are FPGA's
so there hasn't been a push for RTL analysis in the market.
RTL analysis needs to include physical synthesis and some kind of
placement to be really effective. RTL analysis that is just rule
checking is fine but it's rather like grade school compared to college.
Biggest strength of Tera: physical synthesis using a macro structure
they call Teragates. Teragates are like the old macrofunctions of
counters, adders, multipliers, n-bit registers, etc. This gives them
tremendous capacity and reasonable run times with rather large gates.
Biggest Weaknesses of Tera: still perceived as marginally useful by the
ASIC customer base who are biased toward the "let's just get to gates
and figure it out there" approach. It's only been accepted by a few
companies and this is really via a VPA-type deal and for internal
standard product type designs.
- [ An Anon Engineer ]
Tera Systems had a big booth this year. They provide free libraries of
large RTL blocks (adders, multipliers, etc.) that their software uses
to provide size and speed estimates. Creating a library for a new foundry
costs money. Their software runs on Windows, Linux or Solaris and they
say they can synthesis 600K gates in 30 minutes. New for this year is
hierarchical timing analysis, like ILM stuff all done in one step. They
plan on adding capabilities for power and IR drop but it's not here yet.
- John Weiland of Intrinsix
I worked very closely with the Tera Systems R&D people on TeraForm a
couple of years ago to help define/refine their datapath capabilities,
but we went our separate ways when they determined there wasn't enough
market demand to justify their resources.
I can say I was very impressed with the functionality of TeraForm when I
was working with it a couple of years back, but I have little insight
into the accuracy of their prototypes and can't compare it to their
competition. One thing I simply loved about their tool was the way they
graphically presented the logical gate structure of RTL in their
Teragate schematics."
- [ An Anon Engineer ]
Basically we got forced into doing an eval of TeraForm because our
silicon provider LSI Logic requires their customers to either submit
their RTL or provide a TeraForm workspace for LSI to analyze. Since we
cannot release our RTL, we had to provide a TeraForm workspace to LSI
Logic, so doing an evaluation with the plan to purchase the tool seemed
to be the best approach.
Overall, I was not impressed with the tool. We have taped out several
chips based on the current RTL code structure, so I have a fairly good
idea where to expect difficult timing closure. The TeraForm tool did
not identify any of these areas. Instead the tool identified code
structures (medium size MUX structures) as fatal coding problems. This
same code has been in several chips and has never appeared on the timing
closure radar screen.
- [ An Anon Engineer ]
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