( DAC 03 Item 28 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Icinergy SoCarchitect
FLOOR POLISH: Noting how wildly successful First Enounter was inspired
Icinergy to join the business. What's their differentiating advantage?
Price. It's a heck of a lot cheaper than First Encounter and it does
the job. The downside that Icinergy faces here is that Cadence has been
stiching all sorts of hooks for all its other tools to play nice with
First Encounter. SoCarchitect doesn't have this back door access to
the panoply of Cadence tools that First Encounter has. But, hey, for
the price, SoCarchitect users aren't complaining.
The Icinergy SoCarchitect evaluation was a step to improve our design
flow by adding floorplan capability, as at the time, we had none. There
were different floorplanner tools available in the market.
What distinguished SoCarchitect was its RTL floorplanning capability and
its price. We were also interested in the capability of generating
timing constraints to be used for synthesis. Running the tool at the
top level with the pin file and clock definitions didn't generate much
result. But, at the block level, I was able to read in the design and
pin file, by defining the clock domains at the top, was able to generate
block level constraints. Our other goal at the time was to generate
PDEF to be read in by PhysOpt. At the beginning there were some format
problems. But, Icinergy's support was fast to fix the problems. This
of course didn't make our system administrator too happy (multiple
downloads).
To summarize, the SoCarchitect was an addition to our front end design
flow -- a fast way of generating physical data. It also was
complementary to our back end tool. I used the PDEF generated by
SOCarchitect in First Encounter instead of starting from scratch!
- Jamileh Davoudi of SiRF Technology
Here is the scoop: Most other floor planners are trying to get into the
digital backend starting from low information and getting into timing.
Icinergy tool (SoCarchitect - now the SoC Plan) is a simple floorplanner
that is supposed to be used by chip architects and top level front end
designers who have limited knowledge about the physical world. The tool
can input text, Verilog, GDSII for hard macros, and many other formats
that you can ask the vendor for... The intent is to provide a fast,
easy and complete tool to people who are looking at a chip from 3000
miles down.
Even so this was the intention of the development team. I know about a
few successful stories of chip leads that used the tool as the project
progressed and ended up with a chip that resembled (90-95%) the initial
floorplan done with Icinergy SoC Plan.
SoC Plan is easy to install, learn use, etc. It is a SIMPLE tool, cheap
enough to install many, that can help anybody to create a floorplan.
You can use VISIO but it will be a lot more hand work.
Icinergy can:
- Help generate blocks sizes with aspect ratios that are fixed or
soft, with area that is the same.
- Generate pins/ports and places them on the right side of the block
based on connectivity optimization engine.
- Show you the fly lines for congestion analysis.
- Export data to a powerful router (if you have one).
- Simple things to high level data needs.
I did not use the new products Prototype or Preview so cannot give you
feedback there. I checked their web site and it looks that the
Prototype is going after IC Wizard market...
- Dan Clein of PMC-Sierra
Icinergy SoCarchitect caught my eyes. It looks like a very fast
prototype tool, gives you in no-time a nice datasheet with size, power,
and even a draw of floorplanning. And the really good thing: they
already thought on the stage after synthesis and did some correlations
with leading EDA companies.
- Eli Assoolin of Transchip Israel Research Center Ltd.
Icinergy sells an RTL level floorplanner. It takes gate counts from the
user and uses built-in global router to optimize the floorplan. It
competes with the Aristo router from Monterey and Blast Plan from Magma.
They can do virtual or physical repeater insertion. Most customers are
using Synopsys for implementation.
- John Weiland of Intrinsix
InTime's Time Builder - Didn't look at them. Wish I had.
Icinergy SoCarchitect - Didn't look.
Tera's TeraForm - I like this tool, but mostly as an RTL-to-physical
checker, not as a floorplanner.
Cadence First Encounter - The leading prototype tool. Would like to try
it out in Cadence's full flow.
Monterey Calypso & Aristo IC Wizard - Neither tool is worth the effort.
Synopsys Floorplan Compiler - Best features will be included into
Jupiter. Jupiter will be a leading floorplan/prototype tool when they
incorporate some of the Floorplan Compiler features.
Magma Blast Prototype - Pretty useless without the full Magma flow.
- [ An Anon Engineer ]
You can't really beat Icinergy's SoCarchitect on price and performance.
- Anders Nordstrom of Elliptic Semiconductor
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