( DAC 03 Item 23 ) ----------------------------------------------- [ 01/20/04 ]
Subject: ViASIC, Synplicity Structured ASIC
SLIPPING IN SIDEWAYS: Realizing that their frontal assalt on the Synopsys
Design Compiler RTL synthesis monopoly has gone nowhere, the clever guys
at Synplicity have teamed up with LSI Logic to hatch the "Structured ASIC"
initative. Basically "Structed ASIC" is a rehash of the old Gate Array
days where chip designers only tweak that last two metal layers. It neatly
solves the power grid layout & clock tree issues, boiling chip design down
to a simple routing problem. ViASIC, founded by an ex-Synplicity R&D
engineer, sells a new router (ViaPath) optimized for the "Structured ASIC"
architecture. And Synplicity Synplify ASIC does RTL synthesis for the new
"Structured ASIC" architecture rather nicely, too! Clever. Whether this
will get any real traction in the mainstream ASIC market is anyone's guess.
I recently visited ViASIC to observe a demo of ViaPath.
1) The demos was impressive. If this product really works, being able
to do ASIC's with that level of density with a single layer change
is unprecedented. Of course demos always look good.
2) As with most high end EDA tools, the product still has a way to go
before it is ready for commercial distribution. I noticed a few bugs
during the demo. This usually translates into a lot of bugs when the
customer is trying to drive the tool on their own. Hopefully they'll
not follow the typical EDA industry trend and get it cleaned up before
release.
3) Their focus is on 0.18 u or less. Many companies, particularly those
doing mixed signal like mine, are working at geometries greater than
0.35 u. If it can be made to work with 3 and 4 layer metal 0.35 u
technology, it is a product my company would seriously consider.
Overall I think ViaPath could add significant value to any company
attempting to do high transistor count digital ASIC's.
- Jim Kemerling of Triad Semiconductor
My first impression of ViPath is that it has promise, meaning, it's
worth a second look. If I had more time and need, I would seriously
take it to the next step. I can't commit a project to it without
further study, however, I would consider it worth my time to do that due
diligence since there wasn't anything I saw so far that would indicate a
lack of value or potential.
- Dale Donchin of Analog Devices
I used ViaPath to test a small design and here are my observations. I
had to stop at the end, because I could go on and on...
Strengths:
a) Nice GUI interface
b) Looks like it will display the routing in a meaningful manner
c) Seems to mirror the FPGA design-type tools
d) Via-Based Programming Technology
e) Took in the output from Synplify ASIC without issue
Weaknesses:
(NOTE: Since this software is young, it has a long way to go)
a) Crashes often
b) No "Memory" generator
c) No detailed manual or other documentation
d) No easy way to get an STA from the tool itself. Even an estimate
on the non-placed path delays would be nice.
e) No way yet to do embedded PLDs
f) Came with only one libary, and the timing I got was post-synthesis
(From Synplify ASIC). Cannot get post-placement timing without a
at least a preliminary layout.
g) Seemed somewhat slow on even a small design
h) Not very many options for optimization
i) Routing was displayed, but no timing paths or other useful data
was shown.
The ViaPath tool is in its infancy. (I tested an ALPHA version). It
looks like it has a lot of potential, but it is not ready for normal
consumer use. The technology itself may be OK, but without a more
mature tool flow, it's hard to tell.
- Greg Miller of Flextronics Semiconductors
Structured ASICs == gate array deja vu? Actel shipped a "hard array"
more than a decade ago. Everyone knows that just taking an FPGA and
replacing the programming flip-flops/fuses/flash switches with one via
mask will save a huge amount of area and increase speed. Same for
CPLDs. The interesting question to me is whether these ideas work out
in low power circuits.
- Hank Walker of Texas A&M
Structured ASIC may give Synplicity a chance to finally get into main
stream synthesis market. However, it will be another couple years before
such market materialize and by that time, there is no reason the 800 lbs
Synopsys doesn't provide a decent solution.
- Weikai Sun of Volterra
The Structured ASIC is a neat idea, but it targets a small subset of the
market, and relies heavily on users also buying into LSI Logic services.
The total cost has got to be higher than advertised, but still less than
building a full ASIC from scratch. Didn't look at the others.
- [ An Anon Engineer ]
Synplicity Structured ASIC seems interesting, but haven't looked into if
our chips would actually fit/work with this flow.
- Tomoo Taguchi of Hewlett Packard
Synplify Structured ASIC:
Well, LSI, NEC and Chip Express are going this way, so it's obviously
here to stay. Anything that adds choice has to be good, and alternatives
to $ million mask sets must be worth considering.
However, you have some of the problems you have with FPGAs -- gate count
and performance. And, of course, will the IP and memory configurations
the vendors come up with suit my designs?
They are useful in some areas where an FPGA was typically used -- for
instance, mopping up logic on a board. Any gain these devices are making
in market share are more than offset by the overall decline in the ASIC
market, though.
Will ASIC pick-up when the economy does? Let's hope so - I don't want to
be stuck de-bugging those terrible Altera/Xilinx tools for the rest of my
career!
- Thomas Fairbairn of 3com
I think Synplicity Structured ASIC push is a great idea. Structured
ASICs are the future for low-volume (sub 10K/year) ASIC design. If it
gets to the point that all you do is Structured ASIC, why $pend on DC?
- Kevin Hubbard of Siemens
The Synplicity Structured ASIC push? We like the idea.
- Yuval Itkin of Metalink Ltd.
I think Structured ASIC is an extremely smart, intelligent and an
inexpensive solution to the persistent "turn around time" issues. I
think we will see a lot more of the "Structured ASIC" phrase being
bandied around.
- Nicco Bhabu of Chip Express
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