( DAC 03 Item 22 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Hier Design vs. Synplicity Amplify
MIDGET WRESTLING: Hier Design is this year's newbies and their sweet spot
is taking on Synplicity Amplify in the FPGA floorplanning market. It's
way too early to say how Hier will do, but new blood & competition is always
welcomed by any savvy EDA user. :)
One little point of clarification about FPGA tools. The Hier Design
folks are really in a category by themselves. Their tool is meant for
FPGA floorplanning and it is really like the equivalent of a good ASIC
floorplanner for FPGAs. So in that sense it doesn't compete with
Synplicity's product offerings that I know of.
BTW, the tool from Hier Design is pretty reasonable and will be very
useful once they fill in the gaps.
- [ An Anon Engineer ]
Now we outsource our floorplaning.
- Ji Li of Via Tech.
Hier Design is a very cool product -- fits nicely in this niche market
between FPGA synthesis and place and route. The key advantage over
Synplicity Amplify is that you don't have to keep going back to your
RTL to get the floorplan right and it is much faster than using
Xilinx's floorplan tools.
- [ An Anon Engineer ]
First, the Hier's company name is not too good for the French market,
since it means 'Yesterday' :-)
Since June, I guess Hier's PlanAhead now implements some features that I
would have liked to see at that time. (They told me they were currently
working on most of these issues).
I have a personal vision of this type of tool, both from a designer's
perspective (60% of my time) and from a teacher's perspective (30% of my
time) like when I teach LogicLock in the Altera trainings: I do my best
not to have to floorplan!
Most of the timing improvement tricks we use all the time are not
at all complex in theory, and can be automated, for example, duplication
registers, simple re-timing, and hierarchical placement without
flattening. Physical synthesis should render floorplanning worthless in
that it potentially can do a better job than the human designer who can
have trouble understanding and locating the timing bottlenecks,
especially when routing delays are involved.
I've been selling, using, and teaching EDA tools for over a decade, and
I have yet to see a case where automation didn't win:
- DFT -> automatic scan chains insertion, BIST, formal provers...
- Gate level design -> HDL
- Complex operators inference,
- Manual tests -> assertions
Even RTL starts to show some limitations versus behavioral synthesis.
Since my very personal view is not very enthusiastic towards this class
of tools, I have not spent much effort evaluating them. I don't think
they would bring immediate advantage in our designs, and if I can avoid
using them, honestly, I will. I think my design team is more productive
and creates more added value for our customers when we work at the
architectural and RTL level than at the floorplan level.
- Bertrand Cuzeau of ALSE France
I don't use a lot of the advanced features on Amplify. But here goes...
The biggest benefit I've seen from Amplify is the ability to tell it the
actual FPGA you're mapping the design to as well as constraining the
pins in the constraint file (.pcf). The tool then does a good job on
providing the appropriate buffers/fanout to make everything work without
overkill. Designs that didn't fit with Synplify now fit easily and have
better timing margins.
The timing estimator does a good job, tracking the times I get from the
Xilinx router fairly closely in a very full chip. One of my current
designs is 99% full, has 10% unrelated logic packing and uses 41% of the
block RAMs in a Xilinx VirtexII 6000. Amplify reports my system clock
as 18.580 ns and the Xilinx tool reported 18.358 ns.
I've had less luck with defining areas. When a chip isn't too full,
this seems to work okay and helps with some critical paths. This allowed
me to use a slower speed grade part in the past. However, once the FPGA
gets too full, every time I constrain something within an area, a
problem pops up elsewhere.
I haven't used any other FPGA synthesis tools since I dropped Exemplar's
tools over 4 years ago. Amplify has done a good enough job that I
haven't been looking for a replacement so I can't give an apples-to-
apples comparison.
- Greg Warren of Emulex
Synplicity Amplify ASIC - I talked to Synplicity for a long time, but
they seem much more interested in pushing the Structured ASIC approach.
- [ An Anon Engineer ]
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