( DAC 03 Item 21 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Synplicity Synplify & Identify & Certify
THE FPGA KINGS: With Xilinx and Altera giving away free software, it always
amazes me how successful Synplicity is. They have a fantically loyal user
base who jealously defents their Synplify FPGA synthesis tool and they've
branched out nicely into other FPGA niches with Identify (Bridges2Silicon)
RTL debugging and Ceritify for FPGA partitioning. Synplicity should be
flattered that a new start-up, Hier Design, is going up against their Amplify
FPGA floorplanning tool. At the same time, Synplicity is unsuccessfully
trying to nip at the Synopsys Design Compiler monopoly with its Synplify
ASIC tool, but their Structured ASIC push did get noticable air time at
this year's DAC.
The most important feature of Synplicity's Identify is it links real-
time debugging capability with your RTL SOURCE. We were doing a Audio
DSP encoder/decoder project and this tool help us solved many nasty,
nested bugs. Sometimes I use it as a real-time simulator.
The cons are it will create timing closure problem for you so the APR
turnaround time will be increased dramatically. Sometimes the timing
goal is not achievable after you inserted too many watch points.
In comparison, Identify to is far useful than the Altera's and Xilinx's
tool. Period.
- Hown Cheng of ITE USA
We are just getting to the point where we can probe internal nets
efficiently by bringing them to unused pins. We're getting better with
the Logic Analyzer. We like the idea of Identify. The key thing is, of
course, robustness and flexibility in setting the watchpoints. As yet
we don't have a good feel. I need more than a DAC demo to get a feel
for how useful Identify is...
- [ An Anon Engineer ]
Identify seemed like a useful tool. I've used Actel's Silicon Explorer
for hardware debugging and found it somewhat onerous. I would have to
sort through the netlist to get the signals I was looking for. The
problems would really start when one of my RTL signals would get
optimized out and I would have to resort to looking at the schematics
in technology view in Synplify to figure out what was going on.
If Synplicity's Identify works as advertised, it would greatly assist
the hardware debugging effort. I saw a demo by a couple of Synplicity
sales people but I have yet to use it myself.
- Kent Zickuhr of Lockheed Martin
One of the really neat FPGA tools I saw was Synplicity's Identify RTL
Debugger. It solves the visibility problem when doing FPGA prototyping
of an ASIC and you are trying to figure out what is going on inside the
FPGA. This is the Bridges2Silicon technology they bought last year. I
wish Synplicity hadn't removed the support for 0-in assertions.
- Anders Nordstrom of Elliptic Semiconductor
Identify is not perfect, but it does have it's moments.
To be fair, Synplicity may have "over-hyped" my endorsement a bit.
- Richard Grenier of FoundryNet.com
We bought a license for Certify SC, mainly because of it's automated
handling of clock gates, but we never wound up using it. When we got
it, the mapper (I think) was from an earlier version of Synplify.
That in itself would probably have been fine, but we'd already moved
our constraints to the newer version of Synplify. So we were stuck
with the choice of rewriting the constraint files again (not a small
task for this design), or mucking with the clock gate design to make
it equally applicable to ASIC and FPGA designs. By the time the
Certify mapper caught up, we'd already rewritten the clock gate code so
there was no use for it.
Then they moved the clock gate converters into Synplify & eliminated the
need for Certify SC. This was the very first release of Certify SC, so
I'm not terribly surprised that the codebase wasn't fully sync'd with
their other tools yet.
All of that said, I've got only good things to say about Synplicity.
They've supported their tools well, they're responsive, friendly,
everything you'd expect from a company trying to win and keep market
share. This is a very pleasant contrast from the established players.
When we pointed out the problems we were having with the older mapper,
they gave us access to early versions of the next release using the
newer mapper (a nice gesture, but too risky for us to take them up on
it). When Ceritify SC got EOL'd, they offered to move our license to
a Synplify or straight Certify license for free -- a really nice
touch considering we started using Synplicity because Synopsys changed
their product name from FPGA Compiler to FPGA Compiler II and insisted
that meant we had to buy a whole new license.
I don't have any experience w/ the others. We picked up Certify SC
because we were already using Synplify and it looked like a quick
solution to a problem. Our designs are pretty redundant internally,
so breaking up across multiple FPGAs isn't difficult for us to
do by hand.
- Gregory Best of Trimble Navigation Ltd.
FWIW, I never got Certify to work for partitioning. It is always
downrev (for synthesis) compared to the Synplify Pro tool, and when I
tried to do multi-point synthesis with Certify as a preliminary step to
partitioning, it had problems with mixed language designs -- it would
hang (the FAE got me to that point). After that, I had the latest
version of Synplify Pro with a factory patch for another problem that
wouldn't work on Certify - so I never got back to trying it.
I was ready to drop Certify in favor of just using Synplify Pro and
doing hand partitioning, but one thing led to another and we are now
switching to Mentor for FPGA synthesis.
- [ An Anon Engineer ]
Yes I am a user of Certify. I have been using it on an off for about a
year. The only other product that I somewhat evaluated was Aptix, we
were exploring there prototyping solution and decided to make out own
ASIC emulator.
We made a system with 10 FPGA - mostly Virtex II 6000 parts with a
couple of 8000 parts too. I used Certify to partition a 4 million
"gate" ASIC into 9 of the FPGAs. We architected the FPGA conductivity
similar to the expected ASIC structure.
Overall the tool performed fairly well. I took the approach to do
source level partitioning. This creates a top level source file for
each FPGA. This allows the partitioning to be done once as long as
the inter-FPGA conductivity doesn't change. We could even generate
inter-FPGA timing constraints for the Xilinx P&R tools.
Not too many hiccups with the tool, there were a few bugs found, but
Synplicity's support was great. They would provide a fix or work around
pretty quickly. Of course there is always a feature you would like to
have, but overall the job got done. We created a 25MHz emulation version
of an ASIC that should run at 250MHz.
No major complaints, it's actually a pretty cool tool after you get your
board model setup. The best features are the graphical partitioner and
the automatic pin/signal assignment. The auto partitioning didn't work
for our design, so I would count on it working, unless your design is
simple.
- Tom Bylenok of QuickSilver Technology
Synplify rocks, but I'm actually a true believer in Xilinx's free XST
synthesis tool. XST does an excellent job inferring RAMs (block or
distributed), and most importantly, SRL16 inference results in designs
that are 10-20% more logic efficient. The key advantage of XST over
Synplify is that I can run it on my laptop unplugged (running Linux under
VM-Ware) or on my home Linux workstation away from the FlexLM server.
My results have been almost as good as using Synplify, but no license
hassles. Now if I could just target Stratix devices with XST, too...
- Kevin Hubbard of Siemens
We use Synplicity and it's good for our needs.
- Damien Chardonnereau of Iroc Tech
We are using FPGAs to validate our designs (mostly Xilinx). The platform
is an in-house platform as we found it to be more cost effective and also
to better fit our other system requirements (additional peripheral
components). We are using the Synplicity for the FPGA synthesis.
- Yuval Itkin of Metalink Ltd.
I have used Synplify Pro and Quartus. Coming from using Design Compiler
and have a lot of controls via scripting it was painful to learn both of
the above tools. Counter-intutive as it might sound, less constraints in
Synplify seemed to produce better results. If you come from the DC
world, you might want to slowly add more constraints rather than add a
lot of them and then slowly take them out.
Quartus is an interesting tool. I have some problems in getting to set
false paths and it looks like they utilize them only for timing analyzes.
Seems a little useless if they don't use it for their synthesis and place
and route tools.
I am trying to use FPGA Compiler to see if I can get any better results.
We do not have Synplicity license for Altera. That seems to be a load of
a crap that a tool for synthesis has different licenses for different
FPGA vendors.
- [ An Anon Engineer ]
I like Celoxica & Synplicity.
- Gangadhar of DigiPro Design
I kind of like Synplicity. I stopped by Mentor, but was reviewing their
BIST product only.
- [ An Anon Engineer ]
I like Synplicity's set of tools, but can see Synopsys working their way
back into the market if they can tie in DesignWare features to their new
DC-FPGA tool.
- [ An Anon Engineer ]
I've used Synplify for a few years and have had good luck with it. It
seems to produce dense code that is well optimized for FPGA's. My
biggest complaint with Synplify is getting it to do what you tell it to.
Synplify has a tendency to try to optimise everything, despite
instructions to the contrary.
A good example of this was in an asynchronous clock FIFO design where I
was designing empty-full logic. The comparison of the Read-Write
pointers was registered at the output to produce a FIFO Full indication.
The FIFO Full signal went to several state machines to start data
processing. It was impossible to keep Synplify from replicating this
register multiple times. This resulted in some state machines getting a
Full indication and others not, depending on the relative phases of the
asynchronous clocks on either side of the FIFO. I ended up having to
instantiate a Flip-Flop primitive to make it work.
Another problem I have had with Synplify has been with Flip-Flop
enables. If the underlying primitives have a Flip-Flop clock enable, it
can be very difficult to tell Synplify to use that enable instead of
merging the enable into the input logic cloud.
- Joe Vornbrock of Philips
We are a "Structured ASIC" company so I may be a bit biased here, but
after years of using Design Compiler I have been working with the
Synplify-ASIC tool and I've been generally impressed. The GUI interface
was easy to pick up and it had no problems for an initial smaller design
that I ran for comparison. Particularly nice was the tracing abilities
of the schematic and it's tie-in to the static timing analysis report.
There are differences for those familiar with the DC flow, however none
were major and each was relatively easy to deal with (although some may
beg to differ).
For example, a single .syn file (like .db) is needed per design and
black box Verilog (VHDL) models are required for any instantiated cells
in the design (i/o's, rams, pre-synthesized bist logic, etc.). One bonus
though: scan flops can be used during synthesis *without* an extra
license and the next version (purportedly) will also support scan
stitching.
Synplify has established itself in our RTL handoff flow. It is
installed on all our FAE's laptops and is used primarily for quick
estimates on area and timing before the final customer RTL comes in
house for synthesis (where, by the way, we still use DC in our golden
flow). It is important for us to know the probability of fitting in a
given masterslice (array) size and whether we are in the ballpark
timing-wise. Synplify-ASIC gives us decent results for these estimates.
We have also provided our libraries compiled for Synplify on our
external web site since we found that the FPGA designers out there like
to be able to use a familiar tool in analyzing their RTL before handoff.
In summary, we have yet to have any serious issues arise and have found
the tool to be beneficial in this usage model.
- Jeff Waite of Chip Express
I have been using Synplify / Synplify Pro for the past three years for
FPGA synthesis. I have compared synthesis results against Mentor
Leonardo, but the evaluation was done in June of 2001, and no
comparisons have been done recently.
That comparison of Synplify Pro against Leonardo (HDL designer - prior
to release of Precision) showed 20 to 30% better resource packing with
Synplify Pro over Mentor, with timing estimates about 10% better. I used
two designs for this comparison, one that was mostly logic (no device
specific resources), and the other that had high Block RAM and CLB RAM
use. The 30% difference was observed on the design that was high in
RAM resources. Mentor claimed that Leonardo didn't handle inferred RAM
very well in the version I was evaluating, and if I was to instantiate
a vendor RAM their tool performance would have been comparable.
From what I have seen, the Synplicity tools seem to be better tied in
with FPGA vendors for targeting specific FPGA architectural elements
during synthesis, resulting in better design fit and performance than
other tools. That being said, I have also noticed that the more recent
releases of Synplify Pro version 7.2.0, 7.3.0, and the latest 7.3.3 all
fail to fit a previous completed design with no changes. I have been
told that changes to the Synplify Pro mapper stage to make the tool more
generic are the cause, and I can get the same results by adding compiler
directives to the source to control mapping.
My personal feelings are that two years ago Synplify Pro was the only
tool to use for FPGA synthesis. Today I'm not so sure. I think that
Synplicity has tried to expand their market by addition of tools like
Amplify, and their push into ASIC synthesis, which has distracted their
focus and efforts of FPGA synthesis.
- Michael Dabb of Avocent
We used Synplify most recently for development targeted at the Xilinx
VirtexII-Pro line. The only problems I recall were issues with getting
RAMs included in the right places and building the connections to the
RocketIO (high-speed serial) blocks. But Synplicity's support was top-
notch and our FAE got us through any problems in a matter of hours, not
days.
The performance of the tool was phenomenal - certainly faster than ASIC
synthesis. And the results were at least 10-20% better in area than
Leonardo, Xilinx, and Quartus (we've used all three). We especially
liked not having to tailor our syntax to the compiler like we did for
Quartus. It even recognized our '// Synopsys' directives which helped
us with RTL targeted at both an ASIC and an FPGA.
Synplify's easy front-end made it a snap for ASIC designers to give
their RTL a spin to see how bad it was in an FPGA. And the timing
estimates from Synplify matched reasonably well with post P&R results.
My only complaint is that they don't do the full timing-driven place and
route for me - I'm stuck with Xilinx/Altera tools after synthesis.
- Carl Ramey of StarGen Semiconductor
I tried to use Xilinx XST but I gave up due to poor language support
(need to re-write a lot of RTL code in order for the tool to
understand).
Synplify Pro Strengths:
- Strong language support.
- Very tightly integrate with Xilinx place/route tool (strong
support for forward annotation).
- Ease of use.
- Maybe run time?
Synplify Pro Weaknesses:
- Did not provide full suite of options for timing constraint. There
was a specific timing constraint that I want to apply but the tool
did not provide the option/syntax to apply the constraint. But I
can do this in Synopsys DC easily (I'm more of an ASIC guy than an
FPGA guy). I can't recall what it was right now.
That's all I can think of right now. I will let you know if something
else pops up later.
- Kevin Nguyen of Celite Systems
I have done some comparisons in the past of XST versus Synplify Pro.
That was when ISE4.1i was just out, so it is outdated. At that time the
same RTL implemented with both tools was much denser and had better
timings coming from Synplify Pro. Since I was targeting Virtex-II
devices, I am sure XST is a lot better now.
Synplify gives good feedback on how the RTL is implemented, and what
architecture-specific resources are being targeted, as well doing a fair
job at identifying the optimal structures to utilize. This is a big
benefit when dumping ASIC code into FPGAs.
Probably the biggest benefit of Synplify is their support. Synplicity
is large enough to have a good support structure, but small enough to
get personal attention. In one case the FAE was helping me in my cube,
contacted the VP of the company regarding a problem we were working on,
and within a short time had the appropriate engineer involved and
resolving the problem. I would rank Altera and Mentor okay on support,
and Xilinx as low as you can dig a hole (maybe a slight exaggeration).
XST is probably the optimal choice if the design is not speed or space
constrained - since it is built into the ISE tool.
Some complaints about Synplify Pro: The line numbers tend to be
calculated slightly differently from their editor to their synthesis
engine, sometimes making it difficult to determine exactly which line
the error is on. Black boxes are difficult to debug -- note messages
list most objects as black boxes, so you have to wait for the fitter
sometimes to find out a black box was dropped, and often there is no
indication whatsoever why it was dropped.
I am a little skeptical when it comes to the large license premium for
Synplify Pro over Synplify for the bells and whistles gained... but I am
not in marketing.
All things considered, I would still rank Synplify Pro quite a lot
ahead of the others.
- Tony Zabinski of Intel
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