( DAC 03 Item 20 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Mentor FastScan, LogicVision, TetraMAX, Syntest, Genesys, iRoC
GOT BIST? In the normally quiet test world, Synopsys surprized BIST users
this year by adding its own "SoC BIST" solution to bang heads against Mentor
and the King of BIST, LogicVision. The other two smaller BIST players are
Genesys and iRoC, who focus on built-in repair as an added feature. In terms
of mindshare, ATPG customers tend to lean more towards Synopsys TetraMAX vs.
Mentor FastScan -- probably because of Synopsys package deals rather than it
being a better technology.
Test tools
Advantest was there selling a new type of tester. For years all testers
have required that data be "cyclized". That is, it must be described
such that each input always changes at the same time within the clock
cycle, and each output is sampled at the same time. If this might
happen at various times, each combination of I/O timing had to be
described in a "timeset" and you had to explicitly switch between
timesets. If you had multiple clock domains where the cycle times
weren't just simple multiples of each other, describing the timing in
terms of a single cycle for the overall device was a huge headache if
it was possible at all. To make matters worse, the cycle as seen by the
designer goes from active clock edge to active clock edge, while to
the test engineer it starts at the first time an input is presented
before the active edge. Inexperienced design engineers couldn't
understand what test engineers were talking about when they got to
timing.
Advantest is selling CertiMAX, a tester that can use print-on-change
data (like VCD) rather than requiring that data be cycle driven. Have
all the tester companies just been stupid for using cyclized data for
a generation? Maybe not. The maximum speed for this tester is 125 MHz,
which is really, really slow for a digital tester. It is being sold as
a bench top engineering debugging unit, where at-speed test is not
as important, and the ability to quickly use new vectors as the designer
creates them IS important - good niche marketing.
Syntest sells a complete line of test tools, including logic and memory
BIST tools. They had always teamed with Cadence and I had assumed they
would be purchased by Cadence some day, but Cadence bought the
technology from IBM instead.
LogicVision sells tools (technically it's IP) for built-in-self-test
(BIST) of memories and logic. The key issue in logic BIST is
identifying where to insert extra test points; if you only drive and
monitor registers you'll never find some problems. They have a
relatively new tool that uses BIST to isolate faults, and they say
this is really taking off.
The French company iRoC sells BIST for detecting soft errors. They also
sell services to characterize a technology for soft errors, and then
predict the soft error rate based on the netlist. They also provide
radiation test services. Their tool provides fault tolerant RAM and
logic, using a proprietary technique. They claim their memory BIST has
more advanced repair techniques than LogicVision or Mentor but I didn't
get into details. Like last year, they were giving away a sturdy
walking stick that Friar Tuck might use to defend a drawbridge, except
this one had a steel point on the end. I'm sure airport security wound
up with a big stack of them in a corner somewhere - what were these
guys thinking?
Genesys makes BIST for logic and memories (including CAMs, which they
say are better supported this year). Their memory BIST allows for soft
repair of faults (note that the new Virage memory compilers allow for
both soft and hard repair). Their boundary scan insertion tool is now
hierarchical. They can insert ordinary boundary scan (not P1500, etc.)
around internal blocks and do ATPG on one block at a time. They say
they work with normal ATPG tools to do this; I didn't get to look at
the flow.
Intellitech sells IP for boundary scan partitioning. They can do boundary
scan testing of chips with a desktop box costing only $50K.
ASC sells a boundary scan insertion tool.
- John Weiland of Intrinsix
We use Syntest and are very happy with the tools. There are sometimes
frustrating moments, but have been very happy with the Syntest customer
support and the results.
I did visit with LogicVision at DAC and was a little "surprised" with
some of their suggested solutions to one of our concerns !!! We are very
happy with the Formality as our equivalency checker tool.
- Nicco Bhabu of Chip Express
We use and produce M-BISTeR from iRoC Technologies.
- Damien Chardonnereau of Iroc Tech.
iRoC M-BISTeR
iRoC M-BISTeR supports at-speed testing, diagnostics, redundancy support,
and self-repair. The key feature of this product is the ability to do
self-repair of embedded memories at any time. Support for user patterns
is provided along with a large number of canned patterns. IRoC also
claims to have the smallest area footprint of all M-BIST tools. This
tool definitely deserves further attention.
- [ An Anon Engineer ]
Synopsys SoC BIST and DFT Roadmap
SoC BIST is the new logic BIST test capability from Synopsys that
includes D-BIST (deterministic) and X-BIST ("X" state tolerant). Like
most BIST methods, SoC BIST utilizes a PSPG (pseudo-random pattern
generator) for stimulus and a MISR (multiple input signature register)
or CODEC (compression-decompression circuit) for checking. D-BIST is
based on a full stuck-at model and claims to achieve a 200x reduction
in vectors vs. 20x for X-BIST. Because of the circuitry overhead for
LogicBIST, Synopsys recommends standard scan for designs up to
1 M gates, to carefully consider scan or BIST on designs of 2-5M gates,
and full BIST implementation on designs of 20-50M gates. On a 20M gate
design from ATI, SoC BIST required 2% additional area over traditional
scan. Synopsys showed a beta version of a tester resource checking
utility that flags issues like scan vectors exceeding tester memory
depth, tester pin count, etc. This utility requires a tester
personality file that will be provided by ATE manufacturers. In
addition, a template is provided (an ASCII file) for the user to
construct their own ATE personality file.
There are a few limitations of SoC BIST at this time:
1) doesn't write PrimeTime scripts;
2) not integrated into PhysOpt;
3) must seed the PSPG (not self-contained L-BIST);
and 4) no support for M-BIST.
Although it may not be a severe limitation, SoC BIST does not support
VHDL, nor are there plans to do so.
The basic features of SoC BIST will be available in 2003.06 release of
the tool and the above limitations above will be addressed in the
2003.12 release.
- [ An Anon Engineer ]
Mentor M-BIST
Mentor reiterated the issue of new fault types at the 130nm node and
below now require at-speed testing for detection. Like other memory BIST
tools, M-BIST supports at-speed testing, diagnostics, self-analysis, and
redundancy. Support for user patterns is also provided. Mentor has a tool
called MacroTest for use on designs that don't want to incur the BIST
area penalty. MacroTest takes a user defined memory test pattern and
creates the equivalent scan chain data. Mentor claimed M-BIST speeds of
up to 800Mhz, which is largely due to a pipelined implementation. And
like other memory BIST tools, M-BIST creates DC scripts, memory collars
for Verilog or VHDL, wgl patterns, and a Verilog or VHDL test bench.
- [ An Anon Engineer ]
Mentor LBISTArchitect
Mentor LBISTArchitect provides similar functionality to other logic BIST
tools and supports both deterministic and "X" state tolerant L-BIST.
Implementation overhead was on the order of 3-7%, so Mentor recommends
L-BIST on larger designs (>2M gates). LBISTArchitect appears to be ahead
of the comparable product from Synopsys and should be considered as
strong contender for logic BIST.
- [ An Anon Engineer ]
FastScan is a must tool in our flow. For BIST logic, we have our own
solution. For equivalence check we used to use (up to not so long ago)
the Formality but we decided to change our decision to Verplex (now
Cadence) due to our need to proved Verilog 2000 support.
- Yuval Itkin of Metalink Ltd.
We use FastScan and find it working very well. Companies are pushing
Logic BIST but I think this is a non-working solution since the scan
vectors are generated using pseudo-random HW. It will never go to very
high coverage as opposed to ATPG tools that first do random, then aim
specifically at certain faults, so their coverage it much higher. Also,
ECOs are not well supported in Logic BIST.
- [ An Anon Engineer ]
Now we use TetraMAX and LogicVision BIST.
- Ji Li of Via Tech.
We use Synopsys TetraMAX. Has worked fine for us but then we have tried
it on a small design only. Others have used in larger designs but have
never been able to get ATPG fault grading and logic vector fault grading
results to be combined in TetraMAX. I think it is possible but have not
heard of anyone in my company being successful. Could be wrong and it
might not be possible in TetraMAX. Someone in my group is investigating
this at this point of time.
- [ An Anon Engineer ]
I am focused on DFT so you can apply your own filters to my skew.
I was impressed that Synopsys seems to be getting serious about the
problems of testability from conversations with sales and industry DFT
specialists. Synopsys has had their standard tools, but they seem to be
more willing to discuss shortcomings of their tool suite and are looking
at bolstering their support for memory and logic BIST.
Mentor is still late to the party, trying to push their over-priced,
market-hyped TestKompress tool that simply allows designers who have not
migrated out of the 90s to feel their dated testability methodologies can
still support flat (non-hierarchical) design flows as they drift well
above 1 million gates.
With DFT being pushed under the rug by many IC companies hit hard and
looking for areas to cut, Syntest seems to be one company doing slightly
better than the other DFT focused EDA vendors. Their Turbofault product
still leads the way in accurately estimating fault coverage. LogicVision
is still struggling to regain its leadership position in this small
market segment.
The big problem for DFT is the lack of understanding in many smaller and
medium companies that design with COT systems. I predict a number of
product and company failures when the market turns around and suddenly
new complex chips are discovered to be non-manufacturable. This has
already happened at a number of companies in the past 3 years (RIP
Entridia).
The EDA companies are not primarily to blame for these failures; that
responsibility rests entirely on technical management of each company.
Albeit EDA companies are in business to sell their products, not a
manufacturability solution. The problem is where DFT is glossed over by
uneducated senior technical management that never designed multi-million
gate chips to be manufacturable. They're usually just happy to keep the
peace with their senior designers on product delivery schedules.
- Derek Quinn of Cox.net
TestKompress looks great. FastScan speedup 10x because it is too slow.
TetraMAX also has good improvement.
- Liang-Chi Chen of USC
LogicVision BIST technology looks to be good. In the initial design
stage Atrenta - Spyglass DFT is very good for detecting DFT problems.
- Gangadhar of DigiPro Design
LogicVision BIST and LV Validator
LogicVision has expanded its BIST capability to include logic, memory,
and PLL's. The PLL BIST demo was impressive and a Validator-like test
system was able to easily characterize jitter, open loop gain, lock
range, and lock time. All software is provided, including synthesizable
RTL code for Verilog and VHDL, constraints, and test benches.
Memory BIST (M-BIST) includes a wide variety of test patterns (multiple
march patterns) along with the ability to program a customer specific
pattern. Support for column, row, and bank redundancy is provided. All
software is provided, including synthesizable RTL code for Verilog (VHDL
is not supported at this time), constraints, and test benches.
Logic BIST (L-BIST), like other BIST methods utilizes a PSPG (pseudo-
random pattern generator) for stimulus and a MISR (multiple input
signature register) for checking. LogicVision has a patented "capture-
by-domain" technique for devices with multiple clock domains along with
a technique for handling multi-cycle paths. All software is provided,
including synthesizable RTL code for Verilog and VHDL, constraints,
and test benches.
The LV Validator product demo used an Oak TL955 device that ran at 266Mhz
and contained 8M gates with 90+ embedded memories. The overall demo was
very impressive, especially the schmoo plot capability for embedded
memories. Device access was thru the IEEE1149.1 (JTAG) port for both
L-BIST and M-BIST. The individual embedded memories were easily analyzed
or debugged (failed location information is provided). The level of
TetraMAX support was not clear for LogicVision.
- [ An Anon Engineer ]
I was more interested in BIST tools, so I stopped by LogicVision.
- [ An Anon Engineer ]
SpyGlass seems to offer interesting possibilities for quick checking of
DFT santity. We're looking at that too. We use FastScan for overall
ATPG. Cadence's aquiring IBM's Testbench is interesting. I'll be
watching to see if it becomes a major player or not.
I'd really like to find an equivalence checker that works in our world.
Haven't so far.
- Kevin Jones of Rambus
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