( DAC 03 Item 18 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Axis, Tharas, Quickturn, Pittsburgh, EVE, Aptix, Hardi, Dini Group
BETTER SPEED THROUGH IRON: It seems like there was a proliferation of
interest in Big Iron lately. Verisity just bought Axis and Synopsys just
cut some chummy deal with Tharas. And, as usual, the one everyone competes
against id Cadence's Quickturn boxes. Hardi and Pittsburgh are this year's
newbie in the niche.
I'm an FPGA designer in an ASIC group. We've settled on Hardi's HAPS
prototyping system to model our ASIC at nearly-at-speed performance. If
the ASIC designers knew how to write code that was target to an FPGA, we
could probably run it at full speed. ;-)
We chose Hardi because, in contrast to their rival, Dini Systems, the
board had *no* bells nor whistles. It was just 4 large Xilinx FPGAs in
the highest pin-count package available, with an orthogonal routing
topology that makes it easy to guarantee that we won't have signal
contention problems unless we do something really dopey. It configures
with compact Flash, using Xilinx's SystemAce config file generator. This
has worked without a hitch.
Their claim is 200 MHz capability between chips, but we haven't had the
opportunity to push this yet. We will be trying to pump data through at
132 MHz if we can get up to speed with the internals of the FPGAs.
Their clock routing is simple and elegant, giving us 10 global clocks
than be sourced either externally or from one of the 4 FPGAs.
So far, everything they've promised has been delivered and we are quite
happy with it.
The only thing that wasn't completely "plug-and-play" was the board file
for Certify. I never was able to get the "ifdef" stuff working for the
Clock distribution and ended up just hacking up the file manually to make
the necessary connections. Otherwise, Certify did not recognize that the
input to a clock buffer on the PCB and the output can be treated as the
same signal for purposes of partitioning inter-chip I/Os. Probably
Certify's problem and not Hardi's!
- Kevin Smith of Texas Instruments
The Dini Group? Haven't actually bought anything from them yet, but I
like all of their FPGA - PCI prototype platforms. They quoted a custom
project for me (which was unfortunately cancelled, no fault of
DiniGroup) and I received a fast and competitive quote. I wish Mike Dini
well in his business.
- Kevin Hubbard of Siemens
My only interest this year was hardware emulation. I re-evaluated the
current emulators and to my surprise the newcomer ZeBu would be the
winner in my book. The categories I used to evaluate these emulators
where cost, speed performance, ease of use and gate capacity. EVE's Zebu
came out on top in most of the categorizes. I understand their
architecture is very simple but innovative. I plan to recommend this
tool to the 20,000 engineers at my facility.
- George Gomez of Raytheon
EVE offers a series of products that support acceleration / emulation of
designs from 1 to 12 million gates. They work in both co-sim mode with
the testbench running on popular HDL simulator from Synopsys, Cadence and
Mentor, or with C++ testbench in transaction mode while the design is
running on an FPGA based board. Their second mode is a pure emulation
environment with in-circuit emulation or the testbench running on the
emulation board.
Zebu's performance claims are up to tens of KHz in co-sim mode using HDL
simulation or low MHz running C++ testbench. In emulation mode, their
performance is in the MHz range, they claim. One of their demos at DAC
showed a Tensilica MPEG4 core processing a one-minute clip of the
"Monsters, Inc." movie running at 4 frames per second (said to equate
to about 4MHz) while a DBG software debugger was debugging the embedded
software.
EVE also claims full access to the FPGAs at run-time and demonstrated it
in co-simulation with Modelsim adding internal nodes at run-time through
the Modelsim waveform GUI.
The real news is the costs. They claim that a 1 million gate Zebu costs
about $35K while a 12M gate system is under $400K.
They are targeting designers and not verification teams. They want their
systems to be as common as simulators. At the prices they quoted, this
seems plausible.
The other emulators at DAC were basically the same as last year. None of
them offered anything significantly different from last year.
- [ An Anon Engineer ]
I feel Aptix emulator is good in terms of speed and cost.
- Gangadhar of DigiPro Design
Hardware Accelerators, Emulators and Prototyping Systems
Axis Systems sells something that sounds different from normal emulation;
they apparently map your design onto small processor elements within
FPGAs. They claim this provides big advantages in debug, so that you can
mix hardware and software simulation and also get VCD on demand. They
simulate VHDL or Verilog and you can recompile only a small part of your
design. Their biggest box (which is very small physically) has 100M ASIC
gates (800M FPGA gates) and 2.5 Gig of RAM.
Tharas sells what is apparently the only true hardware accelerator left.
This will give you faster compile times than an emulator (50M ASIC
gates/hr) but probably slower run times. They now accept PSL/Sugar and
integrate with NC-Sim, VCS, Modelsim and Debussy.
Cadence Quickturn have one scheme that I'm not sure I understand. If
you buy a bunch of NC-Sim licenses, the Quickturn box you get will
actually have more gates than you paid for, but to use the extra gates
you must temporarily give up 9 licenses while you're using them.
(I think that's it.)
Aldec sells an emulator board with 60M FPGA gates or about 12M ASIC
gates. You can hook up to 12 board together and you can add cores if
you have any in your design.
Dynalith sells a small inexpensive emulator that supports Modelsim,
NC-Sim, VCS and Silos. It now supports SystemC emulation as well. They
have a separate product for in-system verification that hooks a processor
running C into your system.
The Dini group sells a small emulator boards with big FPGAs on them.
They max out at about 6M ASIC gate capacity and 1 Gig of RAM. It hooks
to PCI or Smart Media. Probing is done with Bridges2Silicon or Xilinx
ChipScope. There is no way to hook it to a software simulator.
Pittsburgh Simulation sells something that sounds pretty unique. It is
an actual hardware simulator. It has a scheduler, logic engine and
memory engine in hardware. It can do 9-state simulation on up to 256M
devices with full setup and hold checks, etc. at about 400 times the
speed of Modelsim on a fast system. The base system comes for 15M gates.
It will be interesting to see if crafting a simulator in steel will help
them pirate a share of the market or if they'll be left cold as penguins.
EVE (Emulation and Verification Engineering) sells a PCI card with 1.5M
ASIC gates and 128 MB of RAM. You can daisy chain up to 8 boards. It
hooks to NC, VCS, and Modelsim and can simulate SystemC simulation (cycle
based or transaction level). You can also plug in an ARM, etc. It can
use JTAG for software debug at 4 MHz. One interesting feature is the
ability to have a C or C++ model at a transaction level communicating
with their board.
Aptix sells a prototyping system with 10M ASIC gates in a box. It hooks
to NC-Sim, VCS or Modelsim. They now allow transaction level programming
and have greater visibility into the guts of the box.
Gidel sells a prototyping board with about 1.5M ASIC gates, 256MB of
external RAM and 140MB of RAM within the FPGAs. It operates at 200 MHz
within the board and 100 MHz between boards. You can stack up to
7 boards. They say they have a unique memory controller and can
interface to Linux or Windows.
ProDesign sells prototyping systems that they say has better visibility
than their competitors but better speed than an emulator. Their largest
system can emulate up to 2.5M ASIC gates and 128MB of RAM, operating at
200 MHz. You can plug other chips (like DSPs) on top of the system.
Hardi Electronics of Sweden sells prototyping systems. Each board can
accommodate 6M-8M ASIC gates, up to 34 clocks per board, and the user
can stack up to 8 boards. RAM goes on daughter cards and is the user's
responsibility. There is a flash disk or each board to load the design.
They provide templates for GUI but there is no interface software. The
200 MHZ boards are smaller than Aptix and cost only $25K with training.
Avery Design sells SimCluster, a tool that allows NC-Sim, Modelsim or
VCS to use multiple processors (up to several dozen). They claim a 5X
speedup with only 6 processors, but of course the key questions here
are how to guarantee that 5 processors are twiddling their thumbs
waiting for an overloaded 6th, and how to minimize network traffic so
that all 6 processors aren't twiddling their thumbs. I wasn't able to
get into this.
- John Weiland of Intrinsix
We use Avery SimCluster within our Jazz DSP regression environment.
Our Jazz DSP is based on a configurable VLIW processor and platform
architecture. SimCluster allows us to scale platform simulations (1 to
N Jazz DSP's) from 2 to X nodes depending on the size of the DSP
platform. We've seen simulation performance improve up to 300% with
respect to VCS compile and run times [at both the RTL and gate-level].
Note that with early releases partitioning was a manual process; this
made the setup steps some work for us, but I'm talking a few extra hours
for most of our test cases (your mileage can vary). Indeed, in our
experience SimClusters manual setup time has been minimal compared to
the typical complex setup of many of the HW acceleration boxes that cost
big $$. I'm told that partitioning is automated in the next release;
once we migrate we'll check out how automated. Overall, we really don't
have any complaints.
As VCS performance and raw compute performance improves, I suspect
SimCluster will allow users to get even more out of their simulator and
computer investment. While SimCluster is not completely transparent, it
is very easily integrated into a standard simulation flow and therefore
accessible to all simulation users. In a past life (or two) we had bought
HW acceleration boxes only to find out they require complex setup, flow
changes, and usually constant baby sitting. Just my $0.02.
- Mark Indovina of Improv Systems
We like what we heard about Axis and we're waiting to see what Verisity
does with it.
- Doron Stein of Cisco Systems
It seems like everyone is doing hardware assisted verification this year
given the number of companies offering emulation or hardware acceleration
boxes.
- Anders Nordstrom of Elliptic Semiconductor
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